IP Library › Granted Patent US 12,255,242
Granted Patent B2
US 12,255,242 · App. 17/587,470 · Granted Mar 18, 2025

Three-dimensional memory device including vertical stack of tubular graded silicon oxynitride portions

Inventors: Adarsh Rajashekhar (Santa Clara, CA); Raghuveer S. Makala (Campbell, CA); Koichi Matsuno (Fremont, CA)
Assignee: Sandisk Technologies Inc.
H01L29/4234H01L29/40117H01L29/792H10B43/27
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Quick Facts
Patent No.
US 12,255,242
App. No.
17/587,470
Filed
Jan 28, 2022
Granted
Mar 18, 2025
Kind
B2
Art Unit
2898
USPC
257/324
Abstract

A semiconductor structure includes an alternating stack of insulating layers and electrically conductive layers, a memory opening vertically extending through the alternating stack, and a memory opening fill structure located in the memory opening and including a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular dielectric spacers laterally surrounding the memory film. The tubular dielectric spacers may include tubular graded silicon oxynitride portions having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film, or may include tubular composite dielectric spacers including a respective tubular silicon oxide spacer and a respective tubular dielectric metal oxide spacer. Each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile.

Claims (25)

1. A semiconductor structure, comprising:

an alternating stack of insulating layers and electrically conductive layers;

a memory opening vertically extending through the alternating stack; and

a memory opening fill structure located in the memory opening and comprising a vertical semiconductor channel, a memory film in contact with the vertical semiconductor channel, and a vertical stack of tubular graded silicon oxynitride portions laterally surrounding the memory film and having a composition gradient such that an atomic concentration of nitrogen decreases with a lateral distance from an outer sidewall of the memory film,

wherein the memory film comprises a dielectric metal oxide blocking dielectric layer; and

wherein each of the electrically conductive layers has a hammerhead-shaped vertical cross-sectional profile such that a vertical extent of each of the electrically conductive layers has a local minimum within a cylindrical volume laterally bounded by outer sidewall segments of the memory opening fill structure.

2. The semiconductor structure of claim 1 , wherein the local minimum is located between a first cylindrical plane including outer sidewalls of the vertical stack of tubular graded silicon oxynitride portions and a second cylindrical plane including inner sidewalls of the vertical stack of tubular graded silicon oxynitride portions.

3. The semiconductor structure of claim 2 , wherein the local minimum is located along a continuous closed shape that is equidistant from the first cylindrical plane in a plan view along a vertical direction.

4. The semiconductor structure of claim 1 , wherein a tubular graded silicon oxynitride portion within the vertical stack of tubular graded silicon oxynitride portions comprises:

a contoured top surface including an inner concave top surface segment and an outer concave top surface segment that are adjoined to each other; and

a contoured bottom surface including an inner concave bottom surface segment and an outer concave bottom surface segment that are adjoined to each other.

5. The semiconductor structure of claim 1 , wherein the memory film comprises a layer stack including a tunneling dielectric layer and a charge storage layer in contact with the tunneling dielectric layer.

6. The semiconductor structure of claim 5 , wherein the dielectric metal oxide blocking dielectric layer comprises an aluminum oxide layer in contact with the vertical stack of tubular graded silicon oxynitride portions.

7. The semiconductor structure of claim 6 , wherein each of the electrically conductive layers is spaced from the dielectric metal oxide blocking dielectric layer by a respective backside blocking dielectric layer.

8. The semiconductor structure of claim 7 , wherein the respective backside blocking dielectric layer is in contact with a respective pair of tubular graded silicon oxynitride portions and the dielectric metal oxide blocking dielectric layer.

9. The semiconductor structure of claim 7 , wherein:

the memory opening fill structure further comprises a vertical stack of silicon oxide portions located between neighboring pairs of one of the electrically conductive layers and one of the tubular graded silicon oxynitride portions; and

the respective backside blocking dielectric layer is in contact with a respective pair of silicon oxide portions within the vertical stack of silicon oxide portions.

10. The semiconductor structure of claim 6 , wherein the dielectric metal oxide blocking dielectric layer comprises:

a straight inner sidewall that vertically extends straight through each of the electrically conductive layers from a top periphery of the straight inner sidewall to a bottom periphery of the straight inner sidewall; and

a laterally undulating outer sidewall having a first lateral thickness at levels of the insulating layers and having a second lateral thickness at levels of the electrically conductive layers that is less than the first lateral thickness.

11. The semiconductor structure of claim 6 , wherein the dielectric metal oxide blocking dielectric layer has a uniform lateral thickness throughout and comprises a straight inner sidewall that vertically extends straight through each of the electrically conductive layers from a top periphery of the straight inner sidewall to a bottom periphery of the straight inner sidewall.

12. The semiconductor structure of claim 6 , wherein the memory film further comprises a silicon oxide blocking dielectric layer in contact with an inner sidewall of the dielectric metal oxide blocking dielectric layer.

13. The semiconductor structure of claim 1 , wherein each of the electrically conductive layers is in direct contact with a respective pair of insulating layers of the insulating layers of the alternating stack, and is in direct contact with a respective pair of tubular graded silicon oxynitride portions of the vertical stack of tubular graded silicon oxynitride portions.

14. The semiconductor structure of claim 1 , wherein a maximum vertical extent of one of the electrically conductive layers within the cylindrical volume is greater than a vertical extent of a horizontally-extending portion of the one of the electrically conductive layers located outside the cylindrical volume and having a uniform thickness along a vertical direction.

Assignments (4)
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 28, 2022
From: RAJASHEKHAR, ADARSH; MAKALA, RAGHUVEER S.; MATSUNO, KOICHI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 058814/0262 →
Continuity (1)
Related Publication 20230246084A1 · Aug 3, 2023
References Cited (78)
US 8455940B2 · Lee · 2013 [cited by examiner]
US 8658499B2 · Makala et al. · 2014 [cited by applicant]
US 9356031B2 · Lee et al. · 2016 [cited by applicant]
US 9397093B2 · Makala et al. · 2016 [cited by applicant]
US 9419012B1 · Shimabukuro et al. · 2016 [cited by applicant]
US 9576975B2 · Zhang et al. · 2017 [cited by applicant]
US 9613977B2 · Sharangpani et al. · 2017 [cited by applicant]
US 9659955B1 · Sharangpani et al. · 2017 [cited by applicant]
US 9659956B1 · Pachamuthu et al. · 2017 [cited by applicant]
US 9691884B2 · Makala et al. · 2017 [cited by applicant]
US 9875929B1 · Shukla et al. · 2018 [cited by applicant]
US 9893081B1 · Kanakamedala et al. · 2018 [cited by applicant]
US 10283513B1 · Zhou et al. · 2019 [cited by applicant]
US 10373969B2 · Zhang et al. · 2019 [cited by applicant]
US 10438964B2 · Makala et al. · 2019 [cited by applicant]
US 10516025B1 · Nishikawa et al. · 2019 [cited by applicant]
US 10804282B2 · Baraskar et al. · 2020 [cited by applicant]
US 10861869B2 · Nakamura et al. · 2020 [cited by applicant]
US 10998331B2 · Zhou et al. · 2021 [cited by applicant]
US 11043537B2 · Takahashi · 2021 [cited by examiner]
US 11049807B2 · Li et al. · 2021 [cited by applicant]
US 11101289B1 · Ueda et al. · 2021 [cited by applicant]
US 11114462B1 · Cui et al. · 2021 [cited by applicant]
US 11171153B2 · Kim · 2021 [cited by examiner]
US 11177280B1 · Rajashekhar et al. · 2021 [cited by applicant]
US 20130252391A1 · Lee et al. · 2013 [cited by applicant]
US 20140225181A1 · Makala et al. · 2014 [cited by applicant]
US 20160043093A1 · Lee et al. · 2016 [cited by applicant]
US 20160086972A1 · Zhang et al. · 2016 [cited by applicant]
US 20160379989A1 · Sharangpani et al. · 2016 [cited by applicant]
US 20170125436A1 · Sharangpani et al. · 2017 [cited by applicant]
US 20170243879A1 · Yu · 2017 [cited by examiner]
US 20180040627A1 · Kanakamedala · 2018 [cited by examiner]
US 20180374866A1 · Makala et al. · 2018 [cited by applicant]
US 20190139973A1 · Zhou et al. · 2019 [cited by applicant]
US 20190214395A1 · Zhang et al. · 2019 [cited by applicant]
US 20190386108A1 · Nishikawa et al. · 2019 [cited by applicant]
US 20200006375A1 · Zhou et al. · 2020 [cited by applicant]
US 20200020715A1 · Nakamura et al. · 2020 [cited by applicant]
US 20200388627A1 · Hopkins et al. · 2020 [cited by applicant]
US 20210143171A1 · Kim et al. · 2021 [cited by applicant]
US 20210159167A1 · Tsutsumi et al. · 2021 [cited by applicant]
US 20210265372A1 · Kanakamedala et al. · 2021 [cited by applicant]
US 20210265385A1 · Rajashekhar et al. · 2021 [cited by applicant]
US 20210327889A1 · Makala et al. · 2021 [cited by applicant]
US 20210327890A1 · Makala et al. · 2021 [cited by applicant]
US 20210327897A1 · Kasai et al. · 2021 [cited by applicant]
US 20210335805A1 · Kai · 2021 [cited by examiner]
US 20210335999A1 · Kai et al. · 2021 [cited by applicant]
US 20220093644A1 · Sharangpani · 2022 [cited by examiner]
US 20220278216A1 · Pitner · 2022 [cited by examiner]
US 20220352199A1 · Mukae · 2022 [cited by examiner]
US 20220352201A1 · Hinoue · 2022 [cited by examiner]
US 20230034157A1 · Kim · 2023 [cited by examiner]
US 20230246084A1 · Rajashekhar et al. · 2023 [cited by applicant]
USPTO Office Communication, Notice of Allowance and Fee(s) Due for U.S. Appl. No. 17/587,518, mailed Jun. 28, 2024, 19 pages. [cited by applicant]
Notification of Transmittal of the International Search Report and Written Opinion of the International Searching Authority for International Patent Application No. PCT/US2022/030506, mailed Oct. 27, 2022, 10 pages. [cited by applicant]
Endoh et al., “Novel Ultra High-Density Memory with a Stacked-Surrounding Gate Transistor (S-SGT) Structured Cell,” IEDM Proc. (2001) 33-36. [cited by applicant]
U.S. Appl. No. 17/064,834, filed Oct. 7, 2020, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/169,987, filed Feb. 8, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/189,153, filed Mar. 1, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/192,463, filed Mar. 4, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/192,603, filed Mar. 4, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/192,668, filed Mar. 4, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/244,186, filed Apr. 29, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/345,831, filed Jun. 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/345,860, filed Jun. 11, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,756, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,789, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/351,811, filed Jun. 18, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/378,196, filed Jul. 16, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/406,493, filed Aug. 19, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/523,418, filed Nov. 10, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/523,447, filed Nov. 10, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/523,487, filed Nov. 10, 2021, SanDisk Technologies LLC. [cited by applicant]
U.S. Appl. No. 17/543,987, filed Dec. 7, 2021, SanDisk Technologies LLC. [cited by applicant]
Kubo, T. et al., “Three-Dimensional Memory Device Including Hammerhead-Shaped Word Lines and Methods of Manufacturing the Same,” U.S. Appl. No. 17/587,518, filed Jan. 28, 2022. [cited by applicant]
Gaind, A.K. et al., “Physicochemical Properties of CVD Silicon Oxynitride from a SiH4—CO2—NH3—H2 System,” J. Electrochem. Soc., vol. 125, No. 1, pp. 139-145, (1978). [cited by applicant]