3D semiconductor device and structure with logic and memory
A 3D device, the device including: a first level including logic circuits; a second level including a plurality of memory circuits, where the first level is bonded to the second level, where the bonded includes oxide to oxide bonds, and where the first level includes at least one voltage regulator circuit.
1. A 3D device, the device comprising:
a first level comprising logic circuits; and
a second level comprising a plurality of memory circuits,
wherein said first level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said first level comprises at least one voltage regulator circuit.
2. The 3D device of claim 1 ,
wherein said second level comprises gate all around memory cells.
3. The 3D device of claim 1 ,
wherein said device comprises redundancy circuits to replace at least one faulty logic circuit.
4. The 3D device of claim 1 ,
wherein said device comprises redundancy circuits to replace at least one faulty memory circuit.
5. The 3D device of claim 1 , further comprising:
a first memory cell; and
a second memory cell,
wherein said second memory cell overlays said first memory cell, and
wherein said first memory cell is self-aligned to said second memory cell, being processed following a same lithography step.
6. The 3D device of claim 1 ,
wherein said plurality of memory circuits comprise a multi-bit memory cell.
7. The 3D device of claim 1 ,
wherein said first level comprises a plurality of decoder circuits.
8. A 3D device, the device comprising:
a first level comprising logic circuits; and
a second level comprising a plurality of memory cells,
wherein said first level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said logic circuits comprise at least one power down control circuit.
9. The 3D device of claim 8 ,
wherein said second level comprises gate all around memory cells.
10. The 3D device of claim 8 , further comprising:
a third level comprising a plurality of non-volatile memory cells,
wherein said third level overlays said second level, and
wherein said second level comprises a plurality of volatile memory cells.
11. The 3D device of claim 8 , further comprising:
a first memory cell; and
a second memory cell,
wherein said second memory cell overlays said first memory cell, and
wherein said first memory cell is self-aligned to said second memory cell, being processed following a same lithography step.
12. The 3D device of claim 8 , further comprising:
a third level comprising a plurality of memory cells, said third level overlaying said second level;
a fourth level overlaying said third level or underlying said first level,
wherein said fourth level comprises memory control circuits.
13. The 3D device of claim 8 ,
wherein said first level comprises differential signaling circuits.
14. The 3D device of claim 8 ,
wherein said second level comprises a thinned substrate, and
wherein said thinned substrate has a thickness less than 20 microns.
15. A 3D device, the device comprising:
a first level comprising logic circuits; and
a second level comprising a plurality of memory circuits,
wherein said first level is bonded to said second level,
wherein said bonded comprises oxide to oxide bonds, and
wherein said logic circuits comprise a plurality of antifuse structures.
16. The 3D device of claim 15 ,
wherein said second level comprises gate all around memory cells.
17. The 3D device of claim 15 ,
wherein said second level comprises at least one memory cell comprising a vertically oriented transistor channel.
18. The 3D device of claim 15 , further comprising:
a first memory cell; and
a second memory cell,
wherein said second memory cell overlays said first memory cell, and
wherein said first memory cell is self-aligned to said second memory cell, being processed following a same lithography step.
19. The 3D device of claim 15 ,
wherein said plurality of memory circuits comprise at least four independently controlled memory arrays.
20. The 3D device of claim 15 ,
wherein said device comprises redundancy circuits to replace a faulty circuit.