Vertically stacked FET with strained channel
A stacked semiconductor device includes a lower semiconductor device that has a backside and includes a flipped upper semiconductor device that has a backside that is opposed to the lower semiconductor device backside. The flipped upper semiconductor device further includes a backside residual semiconductor on insulator (SOI) layer and a stressed dielectric portion thereupon. The stacked semiconductor device may be formed by stacking and bonding the flipped upper semiconductor device to the lower semiconductor device, removing one or more semiconductor on insulator (SOI) layers from the backside of the flipped upper semiconductor device while retaining an exposed backside residual SOI layer of the flipped upper semiconductor device, forming a stressed dielectric layer upon the exposed backside residual SOI layer, and patterning the stressed dielectric layer.
1. A stacked semiconductor device comprising:
a lower semiconductor device comprising a first metallization layer comprising a first through metallization layer interconnect that extends entirely through the first metallization layer; and
a flipped upper semiconductor device comprising a second metallization layer comprising a second through metallization layer interconnect that extends entirely through the second metallization layer, wherein the second through metallization layer interconnect is in contact with the first through metallization layer interconnect and wherein the first through metallization layer interconnect and the second through metallization layer interconnect have opposingly tapered sidewalls; the flipped upper semiconductor device further comprising a flipped transistor comprising a source and a drain each connected to the second metallization layer, a backside channel connected to the source and to the drain, a gate connected to the backside channel, a gate spacer between the gate and the source and between the gate and the drain, and a first stressed dielectric portion upon the backside channel that imparts an intrinsic strain within the backside channel, wherein sidewalls of the first stressed dielectric portion are vertically aligned with the gate spacer therebelow between the gate and the source and the gate and the drain.
2. The stacked semiconductor device of claim 1 , wherein the backside channel is a backside residual SOI layer.
3. The stacked semiconductor device of claim 2 , wherein the first stressed dielectric portion imparts an intrinsic tensile strain within a first portion of the backside residual SOI layer.
4. The stacked semiconductor device of claim 3 , wherein the first stressed dielectric portion is upon the first portion of the backside residual SOI layer within an n-type field effect transistor (FET) region.
5. The stacked semiconductor device of claim 4 , further comprising:
a second stressed dielectric portion upon a second portion of the backside residual SOI layer within a p-type field effect transistor (FET) region.
6. The stacked semiconductor device of claim 5 , wherein the second stressed dielectric portion is located vertically in line with the second portion of the backside residual SOI layer and imparts an intrinsic compressive strain within the second portion of the backside residual SOI layer.
7. The stacked semiconductor device of claim 6 , wherein a top surface of the second stressed dielectric portion is coplanar with a top surface of the first stressed dielectric portion.
8. The stacked semiconductor device of claim 2 , wherein the first stressed dielectric portion is located vertically in line with an underlying first channel region of the backside residual SOI layer and imparts an intrinsic tensile strain within the underlying first channel region.
9. The stacked semiconductor device of claim 8 , wherein the first stressed dielectric portion is upon the backside residual SOI layer within an n-type field effect transistor (FET) region.
10. The stacked semiconductor device of claim 9 , further comprising:
a second stressed dielectric portion is upon the backside residual SOI layer within a p-type field effect transistor (FET) region.
11. The stacked semiconductor device of claim 10 , wherein the second stressed dielectric portion is located vertically in line with an underlying second channel region of the backside residual SOI layer and imparts an intrinsic compressive strain within the underlying second channel region.
12. The stacked semiconductor device of claim 11 , wherein a top surface of the second stressed dielectric portion is coplanar with a top surface of the first stressed dielectric portion.
13. A stacked semiconductor device comprising:
a lower semiconductor device comprising a first metallization layer comprising a first through metallization layer interconnect that extends entirely through the first metallization layer; and
a flipped upper semiconductor device comprising a second metallization layer comprising a second through metallization layer interconnect that extends entirely through the second metallization layer and is in contact with the first through metallization layer interconnect, wherein the first through metallization layer interconnect and the second through metallization layer interconnect have opposingly tapered sidewalls; the flipped upper semiconductor device further comprising a flipped transistor comprising a source and a drain each connected to the second metallization layer, a backside residual semiconductor on insulator (SOI) layer connected to the source and to the drain, a gate connected to the backside residual SOI layer, a gate spacer between the gate and the source and between the gate and the drain; a first stressed dielectric portion upon the backside residual SOI layer that imparts an intrinsic tensile strain within an underlying first channel region of the backside residual SOI layer, wherein the first stressed dielectric portion is vertically aligned with the source and a sidewall of the first stressed dielectric portion is vertically aligned with the gate spacer therebelow between the gate and the source; and a second stressed dielectric portion upon the backside residual SOI layer that imparts an intrinsic compressive strain within an underlying second channel region of the backside residual SOI layer, wherein the second stressed dielectric portion is vertically aligned with the drain and a sidewall of the second stressed dielectric portion is vertically aligned with the gate spacer therebelow between the gate and the drain.
14. A stacked semiconductor device comprising:
a lower semiconductor device comprising a lower interconnect that has first tapered sidewalls; and
a flipped upper semiconductor device comprising an upper interconnect that has second tapered sidewalls oppositely tapered relative to the first tapered sidewalls, the flipped upper semiconductor device bonded to the lower semiconductor device, the flipped upper semiconductor device comprising a flipped transistor comprising a source and a drain, an upper channel connected to the source and to the drain, a gate connected to the upper channel, a gate spacer between the gate and the source and between the gate and the drain, and a stressed dielectric portion directly upon the upper channel that imparts an intrinsic strain within the upper channel, wherein sidewalls of the stressed dielectric portion are vertically aligned with the gate spacer therebelow between the gate and the source and the gate and the drain.