IP Library Granted Patent US 12,310,020
Granted Patent B2
US 12,310,020 · App. 17/715,662 · Granted May 20, 2025

Three-dimensional memory device including a dummy word line with tapered corner and method of making the same

Inventors: Nobuyuki Fujimura (Yokkaichi, JP); Shunsuke Takuma (Yokkaichi, JP); Takashi Kudo (Yokkaichi, JP); Satoshi Shimizu (Yokkaichi, JP); Zhixin Cui (Yokkaichi, JP)
Assignee: Sandisk Technologies, Inc.
H10B43/27H10B41/10H10B41/27H10B41/35H10B41/40H10B43/10H10B43/35H10B43/40
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Quick Facts
Patent No.
US 12,310,020
App. No.
17/715,662
Granted
May 20, 2025
Kind
B2
Abstract

A memory device includes a first alternating stack of first insulating layers and first electrically conductive layers located over a substrate, a memory opening vertically extending through the first alternating stack and having a tapered sidewall surface at a level of one of the first electrically conductive layers, and a memory opening fill structure located in the memory opening and comprising a vertical stack of memory elements and a vertical semiconductor channel. One of the first electrically conductive layers includes a taper-containing electrically conductive layer that is located at a level of the lateral protrusion of the memory opening and has a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.

Claims (16)

1. A method of forming a memory device, comprising:

forming a first alternating stack of first insulating layers and first sacrificial material layers located over a substrate, wherein one of the first sacrificial material layers comprises a composite sacrificial material layer including a primary sacrificial material sublayer including a first sacrificial material and a secondary sacrificial material sublayer including a second sacrificial material that is different from the first sacrificial material;

forming a first-tier memory opening through the first alternating stack;

performing an isotropic recess etch process that isotropically etches the second sacrificial material at a higher average etch rate than the first sacrificial material, wherein a recessed sidewall of the composite sacrificial material layer comprises a tapered recessed surface segment; and

forming a memory opening fill structure within a volume including the first-tier memory opening, wherein the memory opening fill structure comprises a vertical stack of memory elements and a vertical semiconductor channel, and comprises a lateral protrusion having a tapered sidewall surface that is parallel to the tapered recessed surface segment.

2. The method of claim 1 , further comprising replacing the first sacrificial material layers with first electrically conductive layers, wherein one of the first electrically conductive layers comprises a taper-containing electrically conductive layer that is formed in a volume from which the composite sacrificial material layer is removed.

3. The method of claim 2 , wherein the taper-containing electrically conductive layer comprises a dummy word line having a contoured sidewall having a tapered sidewall segment that is parallel to the tapered sidewall surface of the lateral protrusion.

4. The method of claim 1 , wherein the recessed sidewall of the composite sacrificial material layer comprises a cylindrical vertical surface segment that is adjoined to the tapered recessed surface segment.

5. The method of claim 1 , wherein:

the first sacrificial material comprises a first silicon nitride material; and

the second sacrificial material comprises a second silicon nitride material having a higher average etch rate during the isotropic recess etch process than an etch rate of the first sacrificial material during the isotropic recess etch process.

6. The method of claim 1 , further comprising:

forming a second alternating stack of second insulating layers and second sacrificial material layers over the first alternating stack;

forming a second-tier memory opening through the second alternating stack over a volume of the first-tier memory opening;

forming an inter-tier memory opening including volumes of the second-tier memory opening and the first-tier memory opening, wherein the memory opening fill structure is formed within the inter-tier memory opening; and

replacing the first sacrificial material layers and the second sacrificial material layers with first electrically conductive layers and second electrically conductive layers, respectively.

Assignments (5)
SECURITY AGREEMENT Recorded Apr 25, 2025
From: SANDISK TECHNOLOGIES, INC.
To: JPMORGAN CHASE BANK, N.A., AS COLLATERAL AGENT
Reel/Frame 071050/0001 →
PARTIAL RELEASE OF SECURITY INTERESTS Recorded Apr 25, 2025
From: JPMORGAN CHASE BANK, N.A., AS AGENT
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 071382/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 31, 2024
From: SANDISK TECHNOLOGIES LLC
To: SANDISK TECHNOLOGIES, INC.
Reel/Frame 069796/0423 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 25, 2022
From: CUI, ZHIXIN
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 060897/0159 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 7, 2022
From: FUJIMURA, NOBUYUKI; TAKUMA, SHUNSUKE; KUDO, TAKASHI; SHIMIZU, SATOSHI
To: SANDISK TECHNOLOGIES LLC
Reel/Frame 059535/0368 →
Continuity (1)
Related Publication 20230328981A1 · Oct 12, 2023
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