Semiconductor chip and semiconductor package including the same
A semiconductor package includes: a semiconductor chip including a front end of line (FEOL) layer and a first back end of line (BEOL) layer disposed on the FEOL layer; and a printed circuit board including a wiring layer and a second BEOL layer disposed on the wiring layer, wherein the semiconductor chip is mounted on the printed circuit board so that the first and second BEOL layers are connected to each other while facing each other, and the second BEOL layer includes a wiring for power transmission.
1. A semiconductor package comprising:
a semiconductor chip including a front end of line (FEOL) layer and a first back end of line (BEOL) layer disposed on the FEOL layer; and
a printed circuit board including a wiring layer and a second BEOL layer disposed on the wiring layer,
wherein the semiconductor chip is mounted on the printed circuit board so that the first and second BEOL layers are connected to each other,
the second BEOL layer includes a wiring for power transmission, and
the first BEOL layer is between the FEOL layer and the second BEOL layer.
2. The semiconductor package of claim 1 , wherein the wiring for power transmission is a wiring for transmitting power to the semiconductor chip.
3. The semiconductor package of claim 1 , wherein the first BEOL layer is disposed adjacent to a bottom side of the semiconductor chip, and
the second BEOL layer is disposed adjacent to a top side of the printed circuit board.
4. The semiconductor package of claim 1 , wherein the FEOL layer includes a first circuit unit including a plurality of first transistor elements and a second circuit unit including a plurality of second transistor elements,
the first and second BEOL layers include first and second wiring units electrically connected to the first and second circuit units, respectively,
the first wiring unit does not include a trace pattern for power transmission interconnecting the first and second circuit units within the first BEOL layer, and
the second wiring unit includes a trace pattern for power transmission interconnecting the first and second circuit units within the second BEOL layer.
5. The semiconductor package of claim 4 , wherein the first wiring unit does not include a trace pattern for power transmission interconnecting at least two of the plurality of first transistor elements and a trace pattern for power transmission interconnecting at least two of the second transistor elements within the first BEOL layer, and
the second wiring unit includes a trace pattern for power transmission interconnecting at least two of the plurality of first transistor elements and a trace pattern for power transmission interconnecting at least two of the second transistor elements within the second BEOL layer.
6. The semiconductor package of claim 1 , wherein the first BEOL layer includes a plurality of metal layers, and
a first metal layer closest to the FEOL layer among the plurality of metal layers includes a trace pattern for signal transmission, but does not include a trace pattern for power transmission.
7. The semiconductor package of claim 6 , wherein the trace pattern for power transmission that is not included in the first metal layer includes at least one of a trace pattern for a positive supply voltage (VDD) and a trace pattern for a negative supply voltage (VSS).
8. The semiconductor package of claim 6 , wherein the first metal layer includes a via pattern for power transmission electrically connected to the wiring for power transmission of the second BEOL layer.
9. The semiconductor package of claim 8 , wherein the via pattern for power transmission that is included in the first metal layer includes at least one of a via pattern for a positive supply voltage (VDD) and a via pattern for a negative supply voltage (VSS).
10. The semiconductor package of claim 1 , wherein the second BEOL layer includes one or more insulating layers and one or more metal layers, and
the one or more insulating layers include an organic insulating material.
11. The semiconductor package of claim 1 , wherein the semiconductor chip further includes a redistribution layer disposed on the first BEOL layer, and
the first and second BEOL layers are connected to each other through the redistribution layer.
12. The semiconductor package of claim 1 , further comprising:
a plurality of connection conductors disposed between the printed circuit board and the semiconductor chip and connecting the printed circuit board and the semiconductor chip to each other; and
a plurality of electrical connection conductors disposed on the other surface of the printed circuit board opposing one surface of the printed circuit board on which the semiconductor chip is mounted and connected to the printed circuit board,
wherein each of the plurality of connection conductors includes a solder bump, and
each of the plurality of electrical connection conductors includes a solder ball.
13. The semiconductor package of claim 1 , wherein silicon is not disposed between the first and second BEOL layers.
14. The semiconductor package of claim 13 , wherein a wiring pitch of the second BEOL layer is greater than a wiring pitch of the first BEOL layer.
15. The semiconductor package of claim 1 , wherein the first BEOL layer is spaced apart from the second BEOL layer.
16. A semiconductor package comprising:
a semiconductor chip including a first BEOL layer, and a FEOL layer;
an interposer board including a second BEOL layer; and
a package board including a wiring layer,
wherein the semiconductor chip is mounted on the interposer board,
the interposer board is mounted on the package board,
the first and second BEOL layers are connected to each other,
the second BEOL layer includes a wiring for power transmission, and
the first BEOL layer is between the FEOL layer and the second BEOL layer.
17. The semiconductor package of claim 16 , wherein the interposer board is an organic interposer or an inorganic interposer,
the organic interposer includes a coreless-type board, and
the inorganic interposer includes a silicon interposer.
18. The semiconductor package of claim 16 , further comprising:
a plurality of connection conductors disposed between the semiconductor chip and the interposer board and connecting the semiconductor chip and the interposer board to each other; and
a plurality of first electrical connection conductors disposed between the interposer board and the package board and connecting the interposer board and the package board to each other; and
a plurality of second electrical connection conductors disposed on the other surface of the package board opposing one surface of the package board on which the interposer board is disposed and connected to the package board,
wherein each of the plurality of connection conductors includes a solder bump, and
each of the plurality of first and second electrical connection conductors includes a solder ball.
19. A semiconductor chip comprising:
a FEOL layer including a plurality of circuit units each including a plurality of transistor elements; and
a BEOL layer disposed on the FEOL layer and including a wiring unit electrically connected to the plurality of circuit units,
wherein the wiring unit does not include a trace pattern for power transmission interconnecting at least two of the plurality of circuit units.
20. The semiconductor chip of claim 19 , wherein the wiring unit does not include a trace pattern for power transmission interconnecting at least two of the plurality of transistor elements of at least one of the plurality of circuit units.
21. A semiconductor package comprising:
a semiconductor chip including a FEOL layer and a first BEOL layer disposed on the FEOL layer, the FEOL layer including a first circuit unit including a plurality of first transistor elements and a second circuit unit including a plurality of second transistor elements, and the first BEOL layer including a first wiring unit electrically connected to the first and second circuit units; and
a printed circuit board including a second BEOL layer including a second wiring unit electrically connected to the first wiring unit,
wherein the semiconductor chip is mounted on the printed circuit board,
the first wiring unit does not include a trace pattern for power transmission interconnecting the first and second circuit units within the first BEOL layer,
the second wiring unit includes a trace pattern for power transmission interconnecting the first and second circuit units within the second BEOL layer,
the first BEOL layer is between the FEOL layer and the second BEOL layer.
22. The semiconductor package of claim 21 , wherein the first wiring unit does not include a trace pattern for power transmission interconnecting at least two of the plurality of first transistor elements within the first BEOL layer, and
the second wiring unit includes a trace pattern for power transmission interconnecting at least two of the plurality of first transistor elements within the second BEOL layer.
23. The semiconductor package of claim 21 , wherein the first wiring unit does not include a trace pattern for power transmission interconnecting at least two of the plurality of second transistor elements within the first BEOL layer, and
the second wiring unit includes a trace pattern for power transmission interconnecting at least two of the plurality of second transistor elements within the second BEOL layer.