Apparatus and method for fabricating multi-die interconnection using lithography process
A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
1 . A method of integrated circuit fabrication comprising:
lithographically fabricating a plurality of die within a semiconductor substrate, the plurality of die comprising a first die defining a plurality of die edges; and
lithographically fabricating a plurality of inter-die connections, comprising:
arranging a first die reticle overlapping a first die edge of the first die;
arranging a second die reticle overlapping a second die edge of the first die; and
exposing, with a lithography system, the first and second die reticles.
2 . The method of claim 1 , wherein lithographically fabricating a plurality of inter-die connections further comprises:
arranging a third die reticle overlapping a third edge of the first die; and
exposing the third die reticle with the lithography system.
3 . The method of claim 1 , wherein, during exposure with the lithography system, both the first and second die reticles overlap a third die edge of the first die.
4 . The method of claim 1 , wherein arranging the first die reticle comprises: setting a position of the first die reticle offset from a center of the first die.
5 . The method of claim 1 , wherein the first and second die reticles are exposed contemporaneously.
6 . The method of claim 1 , wherein exposure with the lithography system fabricates inter-die connections crossing each die edge of the first die.
7 . The method of claim 1 , wherein the first and second die edges are adjacent.
8 . The method of claim 1 , wherein the plurality of die comprises a subset of peripheral die along a periphery of the semiconductor substrate, wherein the first die is an element of the subset.
9 . The method of claim 1 , wherein the plurality of die comprises: a subset of peripheral die along a periphery of the semiconductor substrate and a remainder of die, wherein the remainder of die comprises the first die.
10 . The method of claim 1 , wherein the first die comprises a self-correcting logic device.
11 . The method of claim 1 , further comprising: providing a protective barrier which surrounds the first die.
12 . The method of claim 11 , wherein the protective barrier comprises a seal ring, wherein a subset of inter-die connections of the plurality, associated with the first die, terminate at the first die inside the seal ring.
13 . A method of integrated circuit fabrication comprising:
lithographically fabricating a plurality of die within a semiconductor substrate, the plurality of die comprising a first die defining a die boundary; and
lithographically fabricating inter-die connections across each edge of the die boundary of the first die.
14 . The method of claim 13 , further comprising: providing a seal ring which surrounds a die region of the first die, wherein the seal ring defines the die boundary.
15 . The method of claim 13 , wherein the die boundary is defined based on a set of scribe lines of the semiconductor substrate.
16 . The method of claim 13 , wherein the plurality of die comprises: a subset of peripheral die along a periphery of the semiconductor substrate and a remainder of die, wherein the remainder of die comprises the first die.
17 . The method of claim 13 , wherein lithographically fabricating the inter-die connections comprises: exposing, with a lithography system, a photomask which overlaps an edge of the die boundary of the first die.
18 . The method of claim 13 , wherein lithographically fabricating the inter-die connections across each edge of the die boundary comprises:
setting a photomask at a position which is offset from a center of the first die towards a respective edge; and
exposing the photomask with a lithography system to form a set of inter-die connections along the respective edge.
19 . The method of claim 18 , wherein the inter-die connections are fabricated contemporaneously.
20 . The method of claim 13 , wherein the plurality of die comprises a second, third, fourth, and fifth die, each adjacent to a respective edge of the die boundary of the first die.