Stacked CMOS image sensor
View Patent ↗Various embodiments of the present disclosure are directed towards a stacked complementary metal-oxide semiconductor (CMOS) image sensor in which a pixel sensor spans multiple integrated circuit (IC) chips and has only a first gate dielectric thickness at a first IC chip at which a photodetector of the of the pixel sensor is arranged. Further, the pixel sensor has only one or more second gate dielectric thicknesses at a second IC chip that is stacked with the first IC chip, and the one or more second gate dielectric thicknesses is/are less than or equal to the first gate dielectric thickness. The first and second gate dielectric thicknesses correspond to transistors of the pixel sensor, which form a pixel circuit of the pixel sensor configured to facilitate readout of the photodetector.
1 . A method for forming an image sensor, the method comprising:
forming a first integrated circuit (IC) chip, wherein the forming comprises:
forming a photodetector in a first substrate;
forming a first transistor on the first substrate, adjacent to the photodetector, wherein the photodetector and the first transistor form a first pixel-sensor portion, and wherein the forming of the first transistor comprises:
depositing a dielectric protection layer covering the photodetector and having a first thickness;
depositing a gate electrode layer covering the dielectric protection layer; and
patterning the gate electrode layer to form a gate electrode separated from the first substrate by the dielectric protection layer; and
forming a first interconnect structure covering the first transistor and the photodetector, and further electrically coupled to the first transistor;
forming a second IC chip, wherein the second IC chip comprises:
forming a plurality of second transistors on a second substrate, wherein the plurality of second transistors form a second pixel-sensor portion; and
forming a second interconnect structure covering and electrically coupled to the plurality of second transistors; and
bonding the first and second IC chips together such that the first and second pixel-sensor portions are stacked and electrically coupled together to form a pixel sensor;
wherein the dielectric protection layer persists at covering the photodetector after the bonding, wherein the first transistor comprises a gate dielectric layer with the first thickness and corresponding to a portion of the dielectric protection layer, and wherein the plurality of second transistors comprise individual gate dielectric layers with second thicknesses less than or equal to the first thickness.
2 . The method according to claim 1 , wherein the bonding is performed by bonding in which metal pads respectively of the first and second IC chips are bonded together at an interface and dielectric layers respectively of the first and second IC chips are bonded together at the interface.
3 . The method according to claim 1 , wherein the first thickness extends from the gate electrode of the first transistor to the first substrate.
4 . The method according to claim 1 , further comprising:
forming a third IC chip, wherein the third IC chip comprises:
forming a plurality of third transistors on a third substrate, wherein the plurality of third transistors comprise individual gate dielectric layers with third thicknesses less than or equal to each of the first and second thicknesses; and
forming a third interconnect structure covering the plurality of third transistors, wherein the plurality of third transistors and the third interconnect structure form an application-specific integrated circuit (ASIC); and
bonding the second and third IC chips together, such that the second IC chip is between the first and third IC chips and such that the ASIC is electrically coupled to the pixel sensor.
5 . The method according to claim 1 , wherein the forming of the first IC chip comprises forming multiple instances of the first pixel-sensor portion arranged in a grid pattern, wherein the forming of the second IC chip comprises forming multiple instances of the second pixel-sensor portion arranged in a grid pattern, and wherein the multiple instances of the second pixel-sensor portion correspond to the multiple instances of the first pixel-sensor portion with a one-to-one correspondence.
6 . The method according to claim 1 , wherein the second thicknesses are the same as each other and are less than the first thickness.
7 . A method for forming an image sensor, the method comprising:
forming a first integrated circuit (IC) chip that comprises a first pixel-sensor portion, wherein the first pixel-sensor portion comprises a photodetector in a first substrate, a first transistor adjoining the photodetector on a first side of the first substrate, and a dielectric protection layer covering the photodetector on the first side and separating a gate electrode of the first transistor from the first substrate;
forming a second IC chip that comprises a second pixel-sensor portion, wherein the second pixel-sensor portion comprises a plurality of second transistors;
bonding the first and second IC chips together, such that the first and second pixel-sensor portions are stacked and electrically coupled together to form a pixel sensor;
forming a third IC chip that comprises an application-specific integrated circuit (ASIC), wherein the ASIC comprises a plurality of third transistors; and
bonding the second and third IC chips together, such that the second IC chip is between the first and third IC chips and such that the ASIC is electrically coupled to the pixel sensor,
wherein the dielectric protection layer persists, after the bonding of the second and third IC chips together, at covering the photodetector on the first side of the first substrate and at separating the gate electrode of the first transistor from the first substrate, wherein the first transistor has a first gate dielectric thickness that corresponds to a thickness of the dielectric protection layer, wherein the plurality of second transistors share a second gate dielectric thickness different than the first gate dielectric thickness, and wherein a transistor of the plurality of third transistors has a third gate dielectric thickness less than the second gate dielectric thickness.
8 . The method according to claim 7 , wherein the second IC chip comprises a second substrate on which the second pixel-sensor portion is arranged, and wherein the method further comprises:
forming a through substrate via (TSV) extending through the second substrate between the bonding of the first and second IC chips together and the bonding of the second and third IC chips together.
9 . The method according to claim 7 , wherein another transistor of the second pixel-sensor portion has the first gate dielectric thickness, and wherein another transistor of the ASIC has the second gate dielectric thickness.
10 . The method according to claim 7 , wherein another transistor of the ASIC has a fourth gate dielectric thickness less than the third gate dielectric thickness.
11 . The method according to claim 7 , wherein the forming of the first IC chip comprises forming the gate electrode of the first transistor inset into the first substrate.
12 . The method according to claim 7 , wherein the pixel sensor is a four transistor (4T) active pixel sensor (APS).
13 . The method according to claim 7 , wherein the plurality of second transistors comprise a reset transistor, a source-follower transistor, and a select transistor.
14 . The method according to claim 7 , wherein the second gate dielectric thickness is less than the first gate dielectric thickness.
15 . The method according to claim 7 , wherein the gate electrode of the first transistor borders a first side of the photodetector, and wherein the dielectric protection layer extends from the gate electrode to a second side of the photodetector that is opposite the first side of the photodetector with the thickness of the dielectric protection layer being substantially uniform.
16 . A method, comprising:
forming a first IC chip comprising:
a photodetector in a first semiconductor substrate;
a first transistor that borders the photodetector;
an interconnect structure overlying and electrically coupled to the first transistor; and
a dielectric protection layer that separates the interconnect structure from the photodetector and that separates a gate electrode of the first transistor from the first semiconductor substrate;
forming a plurality of second transistors on a second semiconductor substrate;
vertically stacking the first and second semiconductor substrates;
forming a plurality of third transistors on a third semiconductor substrate; and
vertically stacking the third semiconductor substrate with the first and second semiconductor substrates, such that the second semiconductor substrate is between and spaced from the first and third semiconductor substrates,
wherein the photodetector, the first transistor, and the plurality of second transistors form a pixel sensor, wherein the dielectric protection layer, after the vertical stacking of the first and second semiconductor substrates, persists at separating the interconnect structure from the photodetector and at separating the gate electrode from the first semiconductor substrate, wherein each gate dielectric thickness of the plurality of second transistors is inclusively between a gate dielectric thickness of the first transistor and a maximum gate dielectric thickness amongst the plurality of third transistors, and wherein each gate dielectric thickness of the plurality of second transistors is less than the gate dielectric thickness of the first transistor, which corresponds to a thickness of the dielectric protection layer.
17 . The method according to claim 16 , wherein the plurality of third transistors form an application-specific integrated circuit (ASIC) electrically coupled to the pixel sensor.
18 . The method according to claim 16 , wherein the maximum gate dielectric thickness amongst the plurality of third transistors is less than each gate dielectric thickness of the plurality of second transistors.
19 . The method according to claim 16 , wherein the plurality of second transistors comprises a source-follower transistor, wherein a gate electrode of the source-follower transistor is electrically shorted to a source/drain region of the first transistor, and wherein a gate dielectric thickness of the source-follower transistor is less than the gate dielectric thickness of the first transistor.
20 . The method according to claim 16 , wherein the dielectric protection layer extends along an entire width of the photodetector with the thickness of the dielectric protection layer being substantially uniform and equal to the gate dielectric thickness of the first transistor.