Granted Patent B2

US 12,706,680 · App. 17/807,694 · Granted Aug 11, 2026

Inventors: Philip Winterbottom (San Jose, CA); Martinus Bos (San Jose, CA)

Assignee: Celestial AI Inc.

H04B10/801H04B10/2589H04B10/27H04J14/0284

Abstract

Claims (35)

1 . A system comprising:

a first circuit package comprising:

an electronic integrated circuit (EIC) comprising a plurality of first processing elements and a plurality of first message routers; and

a plurality of first intra-chip bidirectional photonic channels, wherein each first intra-chip bidirectional photonic channel directly connects exactly two message routers of the plurality of first message routers;

a second circuit package comprising:

a second EIC comprising a plurality of second processing elements and a plurality of second message routers; and

a plurality of second intra-chip bidirectional photonic channels, wherein each second intra-chip bidirectional photonic channel directly connects exactly two message routers of the plurality of second message routers; and

a plurality of inter-chip bidirectional photonic channels, wherein each inter-chip bidirectional photonic channel directly connects one of the plurality of first message routers to a respective one of the plurality of second message routers;

wherein, for each message router of the plurality of first message routers and of the plurality of second message routers:

the message router is connected to more than one other message routers; and

the message router is configured to:

receive a message originating from an originating processing element;

select a message router from among the more than one other message routers to transmit the message to, the selected message router being on a transmission path from the originating processing element to a destination processing element identified in the message; and

transmit the message to the selected message router over a photonic channel connecting the message router to the selected message router, the photonic channel being one photonic channel of the pluralities of first intra-chip bidirectional photonic channels, second intra-chip bidirectional photonic channels, or inter-chip bidirectional photonic channels.

2 . The system of claim 1 , wherein each of the first and second circuit packages includes an electronic circuit layer in which the respective EIC is implemented and a photonic circuit layer in which the respective intra-chip bidirectional photonic channels are implemented.

3 . The system of claim 2 , wherein each of the first and second circuit packages includes a first semiconductor chip implementing the electronic circuit layer and a second semiconductor chip implementing the photonic circuit layer.

4 . The system of claim 1 , wherein the pluralities of first and second intra-chip bidirectional photonic channels are implemented in the respective circuit packages using optical waveguides in a photonic integrated circuit (PIC) of the respective circuit packages.

5 . The system of claim 4 , wherein each intra-chip bidirectional photonic channels of the plurality of first and second intra-chip bidirectional photonic channels each comprise one or more photonic links in each direction, each photonic link comprising, in the respective PIC, an optical modulator at an input end of the photonic link, a photodetector at an output end of the photonic link, and an optical waveguide connecting the optical modulator to the photodetector.

6 . The system of claim 5 , wherein each message router of the pluralities of first and second message routers includes a photonic-circuit interface for interfacing with one of the bidirectional photonic channels, each photonic-circuit interface comprising a modulator driver for each photonic link with which it interfaces at the input end of the photonic link and a transimpedance amplifier for each photonic link with which it interfaces at the output end of the photonic link.

7 . The system of claim 5 , wherein the plurality of inter-chip bidirectional photonic channels are implemented with optical fiber.

8 . The system of claim 7 , wherein the plurality of first message routers are connected via the plurality of first intra-chip bidirectional photonic channels to connect the plurality of first processing elements into a first intra-chip electro-photonic network of the first circuit package, and the plurality of second message routers are connected via the plurality of second intra-chip bidirectional photonic channels to connect the plurality of second processing elements into a second intra-chip bidirectional photonic network of the second circuit package, and wherein the first and second circuit packages each include one or more optical coupling structures for coupling the first intra-chip electro-photonic network of the first circuit package via the optical fiber to the second intra-chip electro-photonic network of the second circuit package.

9 . The system of claim 8 , wherein the one or more optical coupling structures includes one or more edge couplers in the respective PIC.

10 . The system of claim 8 , wherein the one or more optical coupling structures includes one or more fiber attach units (FAUs) located over grating couplers in the respective PIC.

11 . The system of claim 7 , wherein each inter-chip bidirectional photonic channel of the plurality of inter-chip bidirectional photonic channels is configured to transmit multiplexed optical signals.

12 . The system of claim 11 , wherein the plurality of inter-chip bidirectional photonic channels each comprises directional photonic channels in each direction, each directional photonic channel connecting a first PIC of the first circuit package and a second PIC of the second circuit package, wherein each inter-chip bidirectional photonic channel includes:

in the first PIC, multiple optical modulators to create modulated optical signals at multiple respective wavelengths, a multiplexer to combine the modulated optical signals at the multiple respective wavelengths into a single multiplexed optical signal, and an optical coupling structure to couple the single multiplexed optical signal into the optical fiber; and

in the second PIC, an optical coupling structure to couple the single multiplexed optical signal from the optical fiber into the second PIC, a demultiplexer to demultiplex the single multiplexed optical signal into modulated optical signals at the multiple respective wavelengths, and multiple respective photodetectors to measure the modulated optical signals at the multiple respective wavelengths.

13 . The system of claim 1 , further comprising at least one single-wavelength light source for supplying an optical carrier signal to modulators of the pluralities of first and second intra-chip bidirectional photonic channels, and at least one multiple-wavelength light source for supplying optical carrier signals at multiple wavelengths to groups of modulators of the plurality of inter-chip bidirectional photonic channels.

14 . The system of claim 13 , where the at least one single-wavelength light source and the at least one multiple-wavelength light source comprise light sources integrated into one or more of the first circuit packages or the second circuit package.

15 . The system of claim 13 , where the at least one single-wavelength light source and the at least one multiple-wavelength light source comprise light sources provided externally to the first and second circuit packages and optically coupled via one or more optical fibers to a respective PICs of one or more of the first circuit package or the second circuit package.

16 . The system of claim 1 , further comprising a plurality of additional circuit packages each having an associated EIC with a plurality of associated processing elements, wherein the first, second, and plurality of additional circuit packages are arranged such that the respective elements form a quadrilateral grid.

17 . The system of claim 16 , wherein each pair of immediately adjacent processing elements in the quadrilateral grid are connected via at least one intra-chip bidirectional photonic channel of the pluralities of first and second intra-chip bidirectional photonic channels or at least one inter-chip bidirectional photonic channel of the plurality of inter-chip bidirectional photonic channels, to form an inter-chip electro-photonic network having a quadrilateral mesh topology.

18 . The system of claim 17 , wherein the plurality of inter-chip bidirectional photonic channels are further configured to directly connect pairs of processing elements on opposite edges of the quadrilateral grid to form an electro-photonic network having an extensible wrapped toroidal mesh topology.

19 . The system of claim 1 , wherein each message router of the plurality of first message routers and of the plurality of second message routers is configured to receive the message, convert the message from an optical domain to an electronic domain, select the selected message router, and convert the message back into the optical domain to transmit the message to the selected message router.

20 . The system of claim 19 , wherein each message router of the plurality of first message routers and of the plurality of second message routers are further configured to select the selected message router based in part on a portion of the message associated with routing information.

Assignments (2)

Continuity (2)

References Cited (400)