Semiconductor device with MMIC and pads reducing wire length
A semiconductor device includes: an MMIC having a DC pad; a bias substrate; a plurality of MIM capacitors mounted on the bias substrate; a plurality of pads provided on the bias substrate and respectively connected to overlying electrodes of the MIM capacitors; and a wire connecting the DC pad to any one of the plurality of pads, wherein the plurality of pads are arranged between the DC pad and the plurality of MIM capacitors in a planar view, and extend parallel to a row of the plurality of MIM capacitors laterally arranged side by side.
1 . A semiconductor device comprising:
an MMIC having a DC pad;
a bias substrate;
a plurality of MIM capacitors mounted on the bias substrate;
a plurality of pads provided on the bias substrate and respectively connected to overlying electrodes of the MIM capacitors; and
a wire connecting the DC pad to any one of the plurality of pads,
wherein the plurality of pads are arranged between the DC pad and the plurality of MIM capacitors in a planar view, and extend parallel to a row of the plurality of MIM capacitors laterally arranged side by side, each of the plurality of pads being entirely spaced from each other.
2 . The semiconductor device according to claim 1 , wherein the plurality of MIM capacitors include first to third MIM capacitors arranged in order in a row,
the plurality of pads include first to third pads respectively connected to overlying electrodes of the first to third MIM capacitors,
the first pad opposes the first MIM capacitor,
the second pad opposes the second MIM capacitor, and
the third pad opposes the third MIM capacitor.
3 . The semiconductor device according to claim 2 , wherein the first pad extends to a position opposing the third MIM capacitor from a position opposing the first MIM capacitor,
the third pad extends to a position opposing the first MIM capacitor from a position opposing the third MIM capacitor, and
the second pad extends to a position opposing the first MIM capacitor and a position opposing the third MIM capacitor after branching from a position opposing the second MIM capacitor.
4 . The semiconductor device according to claim 2 , wherein the plurality of MIM capacitors further include a fourth MIM capacitor arranged in a row with the first to third MIM capacitors,
the plurality of pads further include a fourth pad connected to an overlying electrode of the fourth MIM capacitor, and
the fourth pad extends at a position opposing the first to fourth MIM capacitors.
5 . The semiconductor device according to claim 3 , wherein the plurality of MIM capacitors further include a fourth MIM capacitor arranged in a row with the first to third MIM capacitors,
the plurality of pads further include a fourth pad connected to an overlying electrode of the fourth MIM capacitor, and
the fourth pad extends at a position opposing the first to fourth MIM capacitors.
6 . The semiconductor device according to claim 2 , wherein the plurality of MIM capacitors further include fourth to sixth MIM capacitors arranged parallel to the row of the first to third MIM capacitors,
the plurality of pads further include fourth to sixth pads respectively connected to overlying electrodes of the fourth to sixth MIM capacitors and arranged between the DC pad and the first to third MIM capacitors in a planar view, and
the fourth to sixth pads respectively extend at positions opposing the first to third MIM capacitors.
7 . The semiconductor device according to claim 3 , wherein the plurality of MIM capacitors further include fourth to sixth MIM capacitors arranged parallel to the row of the first to third MIM capacitors,
the plurality of pads further include fourth to sixth pads respectively connected to overlying electrodes of the fourth to sixth MIM capacitors and arranged between the DC pad and the first to third MIM capacitors in a planar view, and
the fourth to sixth pads respectively extend at positions opposing the first to third MIM capacitors.
8 . The semiconductor device according to claim 1 , wherein the plurality of pads include two pads adjacent to each other and having an uneven shape, and a projection of one of the two pads is arranged to be fitted into a recess of the other pad.
9 . The semiconductor device according to claim 2 , wherein the plurality of pads include two pads adjacent to each other and having an uneven shape, and a projection of one of the two pads is arranged to be fitted into a recess of the other pad.
10 . The semiconductor device according to claim 3 , wherein the plurality of pads include two pads adjacent to each other and having an uneven shape, and a projection of one of the two pads is arranged to be fitted into a recess of the other pad.
11 . The semiconductor device according to claim 1 , wherein the plurality of MIM capacitors have different capacitances.
12 . The semiconductor device according to claim 2 , wherein the plurality of MIM capacitors have different capacitances.
13 . The semiconductor device according to claim 3 , wherein the plurality of MIM capacitors have different capacitances.
14 . The semiconductor device according to claim 2 , wherein C 1 , C 2 , and C 3 are respectively capacitance values of the first to third MIM capacitors, and C 1 :C 2 :C 3 =4:2: 1.
15 . The semiconductor device according to claim 3 , wherein C 1 , C 2 , and C 3 are respectively capacitance values of the first to third MIM capacitors, and C 1 :C 2 :C 3 =4:2: 1.
16 . The semiconductor device according to claim 1 , further comprising a plurality of ground pads provided on the bias substrate and respectively connected to underlying electrodes of the plurality of MIM capacitors.
17 . The semiconductor device according to claim 2 , further comprising a plurality of ground pads provided on the bias substrate and respectively connected to underlying electrodes of the plurality of MIM capacitors.
18 . The semiconductor device according to claim 3 , further comprising a plurality of ground pads provided on the bias substrate and respectively connected to underlying electrodes of the plurality of MIM capacitors.
19 . The semiconductor device according to claim 1 , further comprising a plurality of via holes penetrating the bias substrate and respectively connected to underlying electrodes of the plurality of MIM capacitors.
20 . The semiconductor device according to claim 2 , further comprising a plurality of via holes penetrating the bias substrate and respectively connected to underlying electrodes of the plurality of MIM capacitors.