IP Library › Granted Patent US 12,690,196
Granted Patent B2
US 12,690,196 · App. 17/851,178 · Granted Jul 21, 2026

Stacked structure, memory device and method of manufacturing stacked structure

Inventor: Koji Tsunekawa (Tokyo, JP)
Assignee: CANON ANELVA CORPORATION
H10B53/00G11C11/221H10B53/30
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Quick Facts
Patent No.
US 12,690,196
App. No.
17/851,178
Filed
Jun 28, 2022
Granted
Jul 21, 2026
Kind
B2
Art Unit
2817
USPC
257/314
Abstract

A stacked structure includes a ferroelectric layer, and a tunnel barrier layer joined to the ferroelectric layer. The main component of the ferroelectric layer is aluminum nitride, and the main component of the tunnel barrier layer is magnesium oxide.

Claims (39)

1 . A stacked structure comprising a ferroelectric layer, a tunnel barrier layer joined to the ferroelectric layer, a first electrode, and a second electrode, wherein the ferroelectric layer and the tunnel barrier layer are arranged between the first electrode and the second electrode, the stacked structure comprising:

an underlying layer; and

a seed layer arranged on the underlying layer, wherein the first electrode is arranged on the seed layer,

wherein a main component of the ferroelectric layer is aluminum nitride, and a main component of the tunnel barrier layer is magnesium oxide,

wherein the underlying layer is made of one of ruthenium and platinum.

2 . The stacked structure according to claim 1 , wherein

the ferroelectric layer has a wurtzite structure, and a (001) surface of the wurtzite structure is along a junction surface between the ferroelectric layer and the tunnel barrier layer.

3 . The stacked structure according to claim 1 , wherein

the tunnel barrier layer has an NaCl structure, and a (111) surface of the NaCl structure is along a junction surface between the ferroelectric layer and the tunnel barrier layer.

4 . The stacked structure according to claim 1 , wherein

the ferroelectric layer has a wurtzite structure, and the tunnel barrier layer has an NaCl structure, and

a (001) surface of the wurtzite structure and a (111) surface of the NaCl structure are along a junction surface between the ferroelectric layer and the tunnel barrier layer.

5 . The stacked structure according to claim 1 , wherein

the first electrode is a lower electrode, and the second electrode is an upper electrode, and

the tunnel barrier layer is arranged between the first electrode and the ferroelectric layer.

6 . The stacked structure according to claim 1 , wherein

the first electrode includes a facing surface that faces the second electrode via the ferroelectric layer and the tunnel barrier layer, the first electrode has an NaCl structure, and a (111) surface of the NaCl structure of the first electrode is along the facing surface.

7 . The stacked structure according to claim 1 , wherein

the ferroelectric layer contains boron at a concentration of 2 at % (inclusive) to 10 at % (inclusive).

8 . The stacked structure according to claim 1 , wherein

the ferroelectric layer contains scandium at a concentration of 5 at % (inclusive) to 45 at % (inclusive).

9 . A memory device comprising a capacitor including a stacked structure defined in claim 1 .

10 . The stacked structure according to claim 1 , wherein the seed layer is made of one of ruthenium, platinum, nickel and titanium.

11 . A method of manufacturing a stacked structure, comprising:

forming an underlying layer by one of ruthenium and platinum;

forming a seed layer on the underlying layer;

forming an electrode on the seed layer; and

forming, on the electrode, layers including a ferroelectric layer and a tunnel barrier layer, which form a junction,

wherein a main component of the ferroelectric layer is aluminum nitride, and

a main component of the tunnel barrier layer is magnesium oxide.

12 . The method according to claim 11 , wherein

the tunnel barrier layer is formed on the ferroelectric layer.

13 . The method according to claim 11 , wherein

the ferroelectric layer is formed on the tunnel barrier layer.

14 . The method according to claim 11 , wherein

the ferroelectric layer has a wurtzite structure, and a (001) surface of the wurtzite structure is along a junction surface between the ferroelectric layer and the tunnel barrier layer.

15 . The method according to claim 11 , wherein

the tunnel barrier layer has an NaCl structure, and a (111) surface of the NaCl structure is along a junction surface between the ferroelectric layer and the tunnel barrier layer.

16 . The method according to claim 11 , wherein the seed layer is formed on the underlying layer by one of ruthenium, platinum, nickel, and titanium.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 28, 2022
From: TSUNEKAWA, KOJI
To: CANON ANELVA CORPORATION
Reel/Frame 060332/0290 →
Priority Claims (1)
JP 2021-107796 · Jun 29, 2021 · national
Continuity (1)
Related Publication 20220415912A1 · Dec 29, 2022
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