IP Library › Granted Patent US 12,550,374
Granted Patent B2
US 12,550,374 · App. 17/857,541 · Granted Feb 10, 2026

Semiconductor device and formation method thereof

Inventors: Hsin-Yi Lee (Hsinchu, TW); Shan-Mei Liao (Hsinchu, TW); Kuo-Feng Yu (Hsinchu County, TW); Da-Yuan Lee (Hsinchu County, TW); Weng Chang (Hsinchu, TW); Chi On Chui (Hsinchu, TW)
Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
H10D30/6735H01L21/31105H01L21/324H10D30/024H10D30/6211H10D30/6757H10D62/121
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Quick Facts
Patent No.
US 12,550,374
App. No.
17/857,541
Granted
Feb 10, 2026
Kind
B2
Abstract

A method of forming a semiconductor device includes forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers, removing the first semiconductor layers to form spaces each between the second semiconductor layers, forming a gate dielectric layer wrapping around each of the second semiconductor layers, forming a fluorine-containing layer on the gate dielectric layer, performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer, removing the fluorine-containing layer, and forming a metal gate on the gate dielectric layer.

Claims (50)

1 . A method of forming a semiconductor device, comprising:

forming a fin over a substrate, the fin comprising alternately stacking first semiconductor layers and second semiconductor layers;

removing the first semiconductor layers to form spaces each between the second semiconductor layers;

forming a gate dielectric layer wrapping around each of the second semiconductor layers;

forming a fluorine-containing layer on the gate dielectric layer;

performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer;

removing the fluorine-containing layer; and

forming a metal gate on the gate dielectric layer.

2 . The method of claim 1 , wherein the fluorine-containing layer is formed using WF 6 and silane as precursors.

3 . The method of claim 1 , wherein the fluorine-containing layer is tungsten.

4 . The method of claim 1 , further comprising:

forming a barrier layer on the gate dielectric layer prior to forming the fluorine-containing layer, wherein the barrier layer comprises TiN, TaN, or Titanium Silicon Nitride (TSN).

5 . The method of claim 4 , further comprising:

removing the barrier layer after the anneal process.

6 . The method of claim 1 , wherein removing the fluorine-containing layer comprises:

using a wet etch using HCl, H 2 O 2 , H 2 O, a combination thereof.

7 . The method of claim 1 , further comprising:

forming an interfacial layer wrapping around each of the second semiconductor layers prior to forming the gate dielectric layer, wherein the annealing process is performed such that the fluorine atoms in the fluorine-containing layer drives into the interfacial layer.

8 . A method of forming a semiconductor device, comprising:

forming channel layers over a first device region and a second device region of a substrate;

forming a gate dielectric layer wrapping around each of the channel layers;

forming a fluorine-containing layer on the gate dielectric layer;

performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer;

removing the fluorine-containing layer; and

forming a metal gate on the gate dielectric layer, wherein forming the metal gate on the gate dielectric layer comprises:

forming a p-type work function metal layer over the gate dielectric layer; and

removing the p-type work function metal layer in the first device region while remaining the p-type work function metal layer in the second device region.

9 . The method of claim 8 , further comprising:

prior to forming the fluorine-containing layer on the gate dielectric layer, forming a barrier layer over the channel layers.

10 . The method of claim 9 , wherein the barrier layer is TaN.

11 . The method of claim 9 , wherein the barrier layer is titanium nitride.

12 . The method of claim 9 , further comprising:

after performing the anneal process, removing the barrier layer.

13 . The method of claim 8 , wherein forming the metal gate on the gate dielectric layer comprises:

after removing the p-type work function metal layer, forming an n-type work function metal layer over the gate dielectric layer.

14 . The method of claim 13 , wherein the n-type work function metal layer wraps around the channel layers.

15 . The method of claim 8 , wherein the p-type work function metal layer is in contact with the gate dielectric layer in the second device region.

16 . The method of claim 8 , wherein forming the fluorine-containing layer over the gate dielectric layer comprises:

using hexafluoride (WF 6 ) and silane (SiH 4 ) as precursors form a tungsten.

17 . A method of forming a semiconductor device, comprising:

forming nanosheets over a substrate;

forming a gate dielectric layer wrapping around each of the nanosheets;

forming a fluorine-containing layer over the gate dielectric layer;

performing an anneal process to drive fluorine atoms from the fluorine-containing layer into the gate dielectric layer;

removing the fluorine-containing layer; and

forming a metal gate on the gate dielectric layer.

18 . The method of claim 17 , further comprising:

prior to forming the fluorine-containing layer on the gate dielectric layer, forming a TaN layer or a Titanium Silicon Nitride (TSN) layer over the gate dielectric layer.

19 . The method of claim 17 , wherein the metal gate comprises an n-type work function metal.

20 . The method of claim 19 , wherein the n-type work function metal is in contact with the gate dielectric layer.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 6, 2022
From: LEE, HSIN-YI; LIAO, SHAN-MEI; YU, KUO-FENG; LEE, DA-YUAN; CHANG, WENG; CHUI, CHI ON
To: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
Reel/Frame 060411/0993 →
Continuity (1)
Related Publication 20240014279A1 · Jan 11, 2024
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