Gate structures in semiconductor devices
A method includes depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor fin. The method further includes depositing an n-type work function metal layer over the high-k gate dielectric layer and performing a passivation treatment on the high-k gate dielectric layer through the n-type work function metal layer. The passivation treatment comprises a remote plasma process. The method further includes depositing a fill metal over the n-type work function metal layer to form a metal gate stack over the high-k gate dielectric layer. The metal gate stack comprising the n-type work function metal layer and the fill metal.
1 . A method comprising:
depositing a high-k gate dielectric layer over a semiconductor structure;
depositing an n-type work function metal layer over the high-k gate dielectric layer, the n-type work function metal layer comprising aluminum;
performing a plasma treatment to implant a passivating species into the high-k gate dielectric layer through the n-type work function metal layer, wherein the plasma treatment forms a passivated region comprising the passivating species in the high-k gate dielectric layer and the n-type work function metal layer, and wherein a ratio of a first average thickness of the passivated region on sidewalls of the semiconductor structure to a second average thickness of the passivated region on a top surface of the semiconductor structure is in a range of 0.8:1 to 0.9:1; and
depositing a fill metal over the n-type work function metal layer.
2 . The method of claim 1 , wherein the plasma treatment is a remote plasma treatment.
3 . The method of claim 2 , wherein the remote plasma treatment is performed in a processing chamber, and wherein the remote plasma treatment comprises:
placing the semiconductor structure in a first region of the processing chamber;
generating a plasma in a second region of the processing chamber; and
separating the first region of the processing chamber and the second region of the processing chamber with a filter such that the semiconductor structure is exposed to an afterglow disposing after of the plasma generated in the second region of the processing chamber.
4 . The method of claim 1 , wherein the plasma treatment is performed at a temperature less than 100° C.
5 . The method of claim 4 , wherein the plasma treatment is performed at a temperature in a range of 15° C. to 87° C.
6 . The method of claim 1 , wherein the passivating species is fluorine or nitrogen.
7 . The method of claim 1 , wherein the plasma treatment is performed directly on the n-type work function metal layer.
8 . The method of claim 1 , further comprising depositing a capping layer over the n-type work function metal layer, wherein the plasma treatment is performed on the n-type work function metal layer through the capping layer.
9 . A method comprising:
depositing a high-k gate dielectric layer over and along sidewalls of a semiconductor structure;
depositing a first work function metal layer over the high-k gate dielectric layer, wherein the first work function metal layer comprises an n-type metal;
depositing a capping layer over the first work function metal layer, wherein the capping layer comprises the n-type metal, wherein a concentration of the n-type metal in the capping layer decreases in a direction away from the first work function metal layer;
introducing a passivating species into the high-k gate dielectric layer through the first work function metal layer and the capping layer, wherein introducing the passivating species comprises a plasma process; and
after introducing the passivating species, depositing fill metal over the first work function metal layer.
10 . The method of claim 9 , wherein the n-type metal is aluminum.
11 . The method of claim 9 , wherein the plasma process is an isotropic process.
12 . The method of claim 9 further comprising prior to depositing the first work function metal layer, depositing a second work function metal layer over the high-k gate dielectric layer, wherein the second work function metal layer comprises a p-type metal, and wherein the first work function metal layer is disposed over the second work function metal layer.
13 . The method of claim 9 further comprising after introducing the passivating species, depositing a conductive liner over the capping layer, wherein the fill metal is deposited over the conductive liner.
14 . The method of claim 9 further comprising:
depositing an adhesion layer over the high-k gate dielectric layer, wherein the first work function metal layer is deposited over the adhesion layer.
15 . The method of claim 14 further comprising:
depositing a sacrificial capping layer over the adhesion layer;
performing an annealing process on the sacrificial capping layer; and
after performing the annealing process, removing the sacrificial capping layer.
16 . A method comprising:
depositing a high-k gate dielectric layer over a semiconductor structure;
forming a gate stack over the high-k gate dielectric layer, wherein depositing the gate stack comprises:
depositing a first work function metal layer comprising an n-type metal;
depositing a capping layer over the first work function metal layer, wherein the capping layer comprises the n-type metal, and wherein a concentration of the n-type metal in a lower region of the capping layer is greater than a concentration of the n-type metal in an upper region of the capping layer;
performing a fluorination treatment on the high-k gate dielectric layer through the first work function metal layer; and
depositing a first fill metal layer over the first work function metal layer.
17 . The method of claim 16 , wherein a concentration of the n-type metal in the capping layer gradually decreases in a direction away from the first work function metal layer.
18 . The method of claim 16 , wherein the fluorination treatment is a remote plasma process.
19 . The method of claim 18 , wherein the remote plasma process is performed at a temperature less than 100° C.
20 . The method of claim 16 , wherein performing the fluorination treatment drives fluorine into the high-k gate dielectric layer.