Nanosheet transistor device with bottom isolation
A method of forming a nanosheet transistor device is provided. The method includes forming a segment stack of alternating intermediate sacrificial segments and nanosheet segments on a bottom sacrificial segment, wherein the segment stack is on a mesa and a nanosheet template in on the segment stack. The method further includes removing the bottom sacrificial layer to form a conduit, and forming a fill layer in the conduit and encapsulating at least a portion of the segment stack.
1 . A nanosheet transistor device, comprising:
a fill layer section on a top surface and at least a portion of opposite sidewalls of a mesa, wherein the mesa is on a substrate;
one or more nanosheet plates above the fill layer section, wherein the fill layer section is beneath at least a portion of the one or more nanosheet plates and extends from a first side of the one or more nanosheet plates to a second side of the one or more nanosheet plates opposite the first side; and
a stack liner section on a portion of opposite sidewalls of the mesa below the fill layer section, wherein the stack liner section separates a gauge block from the substrate.
2 . The nanosheet transistor device of claim 1 , further comprising a spacer layer section on the stack liner section, wherein the fill layer section is on the stack liner section and the spacer layer section.
3 . The nanosheet transistor device of claim 2 , wherein the gauge block is on the spacer layer section.
4 . The nanosheet transistor device of claim 3 , wherein a top surface of the gauge block is above a top surface of the fill layer section on the mesa.
5 . The nanosheet transistor device of claim 4 , further comprising a gate dielectric layer on a top surface of the fill layer section, a top surface of the gauge block, and a portion of a sidewall surface of the gauge block.
6 . The nanosheet transistor device of claim 3 , wherein the fill layer section is a dielectric material selected from the group consisting of a low-k dielectric material, silicon nitride (SiN), silicon oxy carbonitride (SiOCN), and combinations thereof.
7 . The nanosheet transistor device of claim 5 , wherein the gate dielectric layer is a dielectric material selected from the group consisting of silicon oxide (SiO), a high-k dielectric, and combinations thereof.
8 . The nanosheet transistor device of claim 7 , wherein the stack liner section is a dielectric material selected from the group consisting of silicon oxide (SiO), silicon oxynitride (SiON), and combinations thereof.
9 . A nanosheet transistor device, comprising:
a fill layer section on a top surface and at least a portion of opposite sidewalls of a mesa, wherein the mesa is on a substrate;
one or more nanosheet plates above the fill layer section, wherein the fill layer section is beneath at least a portion of the one or more nanosheet plates and extends from a first side of the one or more nanosheet plates to a second side of the one or more nanosheet plates opposite the first side;
a gate dielectric layer on the fill layer section and each of the one or more nanosheet plates; and
a stack liner section on a portion of opposite sidewalls of the mesa below the fill layer section, wherein the stack liner section separates a gauge block from the substrate.
10 . The nanosheet transistor device of claim 9 , wherein the fill layer section has a thickness in a range of about 4 nanometers (nm) to about 15 nm.
11 . The nanosheet transistor device of claim 10 , wherein the gauge block is in direct contact with a portion of the fill layer section.
12 . The nanosheet transistor device of claim 9 , further comprising a spacer layer section on the stack liner section, wherein the spacer layer section separates the gauge block from the stack liner section and the mesa.
13 . A nanosheet transistor device, comprising:
a fill layer section on a mesa, wherein the mesa is on a substrate;
one or more nanosheet plates above the fill layer section, wherein a cross-section of the fill layer section has an upside-down U-shape underneath the one or more nanosheet plates and an H-shape between a first gate structure and a second gate structure;
a gate dielectric layer on the fill layer section and each of the one or more nanosheet plates; and
a stack liner section on a portion of opposite sidewalls of the mesa below the fill layer section, wherein the stack liner section separates a gauge block from the substrate.
14 . The nanosheet transistor device of claim 13 , wherein the fill layer section is a dielectric material selected from the group consisting of silicon nitride (SIN), silicon oxy carbonitride (SIOCN), and combinations thereof.
15 . The nanosheet transistor device of claim 14 , further comprising a conductive gate electrode between the fill layer section and a bottom most nanosheet plate of the one or more nanosheet plates.
16 . The nanosheet transistor device of claim 15 , wherein the gauge block is adjacent to the fill layer section.
17 . The nanosheet transistor device of claim 16 , further comprising a spacer layer section between the gauge block and the stack liner section.