Image sensor device and methods of forming the same
A device is disclosed. The device includes a plurality of pixels disposed over a first surface of a semiconductor layer. The device includes a device layer disposed over the first surface. The device includes metallization layers disposed over the device layer. One of the metallization layers, closer to the first surface than any of other ones of the metallization layers, includes at least one conductive structure. The device includes an oxide layer disposed over a second surface of the semiconductor layer, the second surface being opposite to the first surface, the oxide layer also lining a recess that extends through the semiconductor layer. The device includes a spacer layer disposed between inner sidewalls of the recess and the oxide layer. The device includes a pad structure extending through the oxide layer and the device layer to be in physical contact with the at least one conductive structure.
1. A method for fabricating semiconductor devices, comprising:
forming, over a first surface of a semiconductor layer, a plurality of pixels configured to absorb radiation from a second surface of the semiconductor layer, the second surface of the semiconductor layer being opposite to the first surface of the semiconductor layer;
forming a device layer over the first surface of the semiconductor layer;
forming a metallization layer over the device layer;
forming, through the second surface of the semiconductor layer, a recess laterally separated from the plurality of pixels;
forming a spacer layer extending along inner sidewalls of the recess;
forming a second oxide layer over the second surface with the spacer layer sandwiched between the inner sidewalls and the second oxide layer;
etching the second oxide layer and a portion of the device layer to expose a portion of the metallization layer; and
forming a pad structure electrically coupled to the exposed portion of the metallization layer.
2. The method of claim 1 , wherein the spacer layer has a profile gradually tapered from the first surface to the second surface of the semiconductor layer.
3. The method of claim 1 , further comprising:
depositing a first oxide layer over lining at least the recess; and
patterning, through an etching process, the first oxide layer to form the spacer layer.
4. The method of claim 3 , wherein the etching process includes an anisotropic etching process.
5. The method of claim 1 , wherein the spacer layer covers only corners of the recess.
6. The method of claim 1 , wherein the spacer layer has a greater etching resistivity than the second oxide layer.
7. The method of claim 1 , wherein the spacer layer and the second oxide layer include the same polyethyloxazoline (PEOX), but the spacer layer has a greater etching resistivity than the second oxide layer.
8. The method of claim 1 , wherein the spacer layer and the second oxide layer include the same material selected from a group consisting of: silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (F SG), and combinations thereof, but the spacer layer has a greater etching resistivity than the second oxide layer.
9. The method of claim 1 , wherein the recess has a depth of at least about 2 μm.
10. The method of claim 1 , further comprising:
filling a remaining portion of the recess with a dielectric material;
forming a bump structure extending through the dielectric material to be in contact with the pad structure.
11. A method for fabricating semiconductor devices, comprising:
forming, over a first surface of a semiconductor layer, a plurality of pixels;
forming a plurality of transistors over the first surface of the semiconductor layer;
forming a metallization layer over the plurality of transistors;
forming, through a second surface of the semiconductor layer opposite to the first surface, a recess laterally separated from the plurality of pixels;
forming a spacer layer covering corners the recess and exposing a bottom surface forming an oxide layer over the spacer layer;
forming, in the recess, a pad structure electrically coupled to the metallization layer;
filling a remaining portion of the recess with a dielectric material; and
forming a bump structure extending through the dielectric material to be in contact with the pad structure.
12. The method of claim 11 , wherein the plurality of pixels are configured to absorb radiation from the second surface of the semiconductor layer.
13. The method of claim 11 , wherein the spacer layer includes a first portion closer to the metallization layer and a second portion less closer to the metallization layer, and wherein the first portion has a lateral width wider than a lateral width of the second portion.
14. The method of claim 11 , wherein the spacer layer has an upper surface with an arc-based profile.
15. The method of claim 11 , wherein the spacer layer has an upper surface with a facet-based profile.
16. The method of claim 11 , wherein the spacer layer and the second oxide layer include the same material selected from a group consisting of: silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (F SG), and combinations thereof, but the spacer layer has a greater etching resistivity than the second oxide layer.
17. The method of claim 11 , wherein the spacer layer and the second oxide layer include the same polyethyloxazoline (PEOX), but the spacer layer has a greater etching resistivity than the second oxide layer.
18. A method for fabricating semiconductor devices, comprising:
forming, over a first surface of a semiconductor layer, a plurality of pixels within a first region of the semiconductor layer;
forming a device layer over the first surface of the semiconductor layer;
forming a plurality of metallization layers over the device layer;
forming, through a second surface of the semiconductor layer opposite to the first surface, a plurality of recesses within a second region of the semiconductor layer;
forming a plurality of tapered spacer layers, each of the tapered spacer layers covering only corners of a corresponding one of the plurality of recesses;
forming a plurality of pad structures in the plurality of recesses, respectively,
wherein each of the pad structures is electrically coupled to a corresponding one of the metallization layers;
filling a remaining portion of each of the plurality of recesses with a dielectric material; and
forming a bump structure extending through the dielectric material to be in contact with a corresponding pad structure of the pad structures.
19. The method of claim 18 , wherein the second region is located around a perimeter of the first region.
20. The method of claim 18 , wherein the plurality of tapered spacer layers are made of a material selected from a group consisting of silicon oxide, undoped silicate glass (USG), phosphosilicate glass (PSG), borophosphosilicate glass (BPSG), fluorine-doped silicate glass (F SG), and combinations thereof.