Self-aligned silicide gate for discrete shielded-gate trench power MOSFET
Apparatus and methods for shielded-gate trench power MOSFETs are disclosed herein. The power MOSFETs are fabricated using a self-aligned gate poly silicide to achieve low gate resistance. Accordingly, the power MOSFETs can be used in high speed applications operating with fast transistor switching speeds. Moreover, the self-aligned gate poly silicide processing can be achieved in relatively few processing steps, and thus can avoid the cost and/or complexity associated with conventional silicidation techniques for trench power MOSFETs. In particular, silicidation can include applying a silicide that is self-aligned to a gate oxide without an additional mask.
1 . A method of fabricating a shielded-gate metal-oxide-semiconductor field-effect transistor, comprising:
etching a gate trench in a top surface of a semiconductor layer of a first doping polarity;
forming a semiconductor well in the semiconductor layer and of a second doping polarity opposite the first doping polarity;
forming a source region in the semiconductor well and of the first doping polarity;
contacting the semiconductor well and the source region using a metal contact;
forming in the gate trench a gate shield and a gate region each recessed below the top surface of the semiconductor layer and electrically insulated from the semiconductor layer by a gate oxide, wherein the gate region is formed over the gate shield in the gate trench and electrically insulated from the gate shield;
forming a silicide region over the gate region, the silicide region being aligned to the gate region by the gate oxide;
rapid thermal annealing only at a temperature below 800 degrees Celsius after forming the silicide region; and
besides the rapid thermal annealing, performing thermal processing after forming the silicide region at a temperature of no more than about 650 degrees Celsius to preserve the silicide region.
2 . The method of claim 1 , further comprising applying an intermediate dielectric layer over the gate shield to electrically insulate the gate shield from the gate region.
3 . The method of claim 2 , wherein the dielectric layer comprises an oxide.
4 . The method of claim 1 , wherein the rapid thermal annealing is performed for no more than about 10 seconds.
5 . The method of claim 1 , further comprising forming the silicide region with a maximum vertical depth that does not exceed a maximum vertical depth of a junction of the source region and the semiconductor well.
6 . The method of claim 5 , wherein the first doping polarity is n-type and the second doping polarity is p-type.
7 . The method of claim 1 , further comprising forming a primary upper oxide layer over the silicide region by using plasma-enhanced chemical vapor deposition at no more than 650° C.
8 . The method of claim 7 , further comprising forming a secondary upper oxide layer over the primary upper oxide layer using high-density-plasma chemical vapor deposition at no more than 650° C.
9 . The method of claim 7 , wherein the primary upper oxide layer is formed as sub-layers in multiple iterations to maintain a temperature below 650° C.
10 . The method of claim 1 , further comprising performing backend processing over the silicide region at a temperature of no more than 650° C.
11 . The method of claim 1 , wherein the silicide region is recessed within the gate trench below the top surface of the semiconductor layer.
12 . The method of claim 1 , further comprising forming a metal layer over the semiconductor layer, the metal layer including a source electrode electrically connected to the metal contact.
13 . The method of claim 12 , further comprising forming a drain electrode connected to a bottom surface of the semiconductor layer.
14 . The method of claim 12 , wherein the gate shield is electrically connected to the source electrode.
15 . The method of claim 1 , further comprising forming the gate oxide as a thermal oxide.
16 . The method of claim 1 , further comprising forming the gate oxide using a high-density plasma (HDP).
17 . The method of claim 1 , wherein the gate trench has a depth of at least 1 micrometer relative to the top surface of the semiconductor layer.
18 . The method of claim 1 , wherein the silicide region comprises a cobalt silicide.
19 . The method of claim 1 , wherein the silicide region comprises a titanium silicide.
20 . The method of claim 1 , wherein the first doping polarity is n-type, and the second doping polarity is p-type.