Granted Patent B2

US 12,230,354 · App. 17/971,300 · Granted Feb 18, 2025

Inventors: Jason T. Zawodny (Grand Rapids, MI); Kelley D. Dobelstein (Seattle, WA); Timothy P. Finkbeiner (Boise, ID); Richard C. Murphy (Boise, ID)

G11C7/1006G06F3/061G06F3/0659G06F3/0685G11C7/06G11C7/065G11C7/1036G11C8/12G11C11/4087G11C11/4091G11C11/4096

Abstract

Claims (41)

1. A system, comprising:

a host configured to generate a block of instructions including instructions for a gather operation; and

a controller configured to:

receive the block of instructions; and

execute the gather operation by:

iterating through indices of an index vector stored in a memory device to which the controller is coupled, the indices pointing to respective first vector portions corresponding to the gather operation;

reading the respective first vector portions from an array of the memory device;

merging, in a buffer of the controller, the first vector portions read from the array; and

writing the merged first vector portions to a second vector corresponding to the gather operation, wherein the second vector is stored in the array.

2. The system of claim 1 , wherein the first vector is a source vector and the second vector is a destination vector.

3. The system of claim 1 , wherein the controller is a channel controller coupled to the memory device via a bus.

4. The system of claim 3 , wherein the first vector portions are provided to the channel controller via an out-of-band bus.

5. The system of claim 1 , wherein the first vector has a size larger than a cache size corresponding to the host.

6. The system of claim 1 , wherein the buffer of the controller is a first buffer, and wherein the controller comprises a plurality of additional buffers configured to bin the indices of the index vector.

7. The system of claim 1 , wherein the memory device is one of a plurality of memory devices integrated on a module.

8. The system of claim 1 , wherein the memory device comprises sensing circuitry coupled to the array and configured to perform logical operations in association with performing the gather operation.

9. A system, comprising:

a host configured to generate a block of instructions including instructions for a scatter operation; and

a controller configured to:

receive the block of instructions; and

execute the scatter operation by:

iterating through indices of an index vector stored in an array of a memory device to which the controller is coupled, the indices pointing to respective locations in the array to which respective portions of a first vector corresponding to the scatter operation are to be written;

reading, from the array, a second vector corresponding to the scatter operation, the second vector comprising data to be written at the respective locations in the array to which the respective portions of the first vector correspond; and

writing the first vector to the array, the respective portions of the first vector being written at the respective locations in array pointed to by the respective indices of the index vector.

10. The system of claim 9 , wherein the controller is configured to bin the indices of the index vector in a number of buffers of the controller.

11. The system of claim 10 , wherein the controller is a channel controller located on the host and coupled to the memory device via a bus.

12. The system of claim 9 , wherein the host comprises a scalar processor.

13. The system of claim 9 , wherein the memory device is a processing in memory (PIM) device comprising a PIM execution unit configured to perform PIM operations in association with execution of the scatter operation.

14. The system of claim 13 , wherein the array comprises multiple banks, and wherein the respective locations in the array to which the respective indices of the index vector point are located in at least two different banks.

15. The system of claim 9 , further comprising an out-of-band bus coupling the memory device to the controller.

16. An apparatus, comprising:

a controller configured to execute a gather operation; and

a plurality of memory devices coupled to the controller and storing a plurality of vectors corresponding to the gather operation;

wherein at least one of the plurality of memory devices is configured to receive individual instructions associated with the gather operation at respective banks of a plurality of banks on the at least one memory device;

wherein the controller is configured to control execution of the individual instructions associated with the gather operation on the at least one memory device by binning, in a buffer local to the controller, indices from an index vector stored in the at least one memory device.

17. The apparatus of claim 16 , wherein the plurality of vectors includes a source vector comprising a plurality of source vector portions, wherein the indices of the index vector point to respective locations in the at least one memory device at which the respective source vector portions are stored.

18. The apparatus of claim 17 , wherein the at least one memory device is configured to, in association with executing the gather operation:

perform read operations at the respective locations to obtain the respective source vector portions; and

provide the respective source vector portions to the controller.

19. The apparatus of claim 18 , wherein the at least one memory device is configured to provide the respective source vector portions to the controller via an out of band bus.

20. The apparatus of claim 18 , wherein the controller comprises a reassembly buffer configured to merge the respective source vector portions received from the at least one memory device; and wherein the controller is configured to write the merged respective source vector portions to a target vector in the at least one memory device.

Assignments (2)

Continuity (6)

References Cited (312)