Interconnect structures for semiconductor devices and methods of manufacturing the same
A method for making a semiconductor device includes forming a first patterned structure over an interlayer dielectric. The interlayer dielectric overlays a first source/drain structure and a second source/drain structure. The first patterned structure extends along a first lateral direction and a vertical projection of the first patterned structure is located between the first and second source/drain structures along a second lateral direction perpendicular to the first lateral direction. The method includes reducing a width of the first patterned structure that extends along the second lateral direction. The method includes forming, based on the first patterned structure having the reduced width, contact holes that expose the first source/drain structure and the second source/drain structure, respectively.
1 . A method for making a semiconductor device, comprising:
overlaying a first source/drain structure and a second source/drain structure with an interlayer dielectric, wherein the first source/drain structure and the second source/drain structure are separated from each other along a first lateral direction;
forming a patterned structure over the interlayer dielectric, and interposed between the first source/drain structure and the second source/drain structure along the first lateral direction;
reducing a width of the patterned structure extending in the first lateral direction, thereby increasing a dimension of interconnect structures coupled to the first source/drain structure and the second source/drain structure, respectively; and
exposing, based on the patterned structure having the reduced width, the first source/drain structure and the second source/drain structure; prior to the step of reducing a width of the patterned structure extending in a first lateral direction, further comprising: depositing at least one imaging layer over the interlayer dielectric; and forming a trench in the at least one imaging layer that extends along a second lateral direction perpendicular to the first lateral direction and exposes a central portion of the patterned structure.
2 . The method of claim 1 , wherein the step of reducing a width of the patterned structure further comprises etching the central portion of the patterned structure through the trench, while clamping end portions of the patterned structure with the at least one imaging layer.
3 . The method of claim 1 , further comprising depositing a metal material over at least the exposed first source/drain structure and the exposed second source/drain structure to form a first interconnect structure and a second interconnect structure that electrically connect to the first and second source/drain structures, respectively.
4 . The method of claim 3 , wherein the first and second interconnect structures are electrically isolated from each other by a portion of the interlayer dielectric that is vertically projected from the patterned structure that has the reduced width in the first lateral direction.
5 . The method of claim 1 , wherein an amount of the reduced width is at least about 1 nanometer (nm).
6 . The method of claim 1 , subsequently to the step of reducing a width of the patterned structure extending in a first lateral direction, further comprising:
depositing at least one imaging layer over the interlayer dielectric; and
forming a trench in the at least one imaging layer that extends along a second lateral direction perpendicular to the first lateral direction and exposes a central portion of the patterned structure.
7 . The method of claim 1 , wherein the step of exposing the first source/drain structure and the second source/drain structure further comprises etching the interlayer dielectric based on a dry etching process that includes an etchant selected from the group consisting of: carbon tetrafluoride (CF 4 ), hexafluoro-1,3-butadiene (C 4 F 6 ), octafluorocyclobutane (C 4 F 8 ), and oxygen (O 2 ).
8 . The method of claim 1 , wherein the step of reducing a width of the patterned structure further comprise performing at least one of a dry etching process or a wet etching process.
9 . The method of claim 8 , wherein the wet etching process includes applying at least one of an acid-based etchant or an alkaline-based etchant on the patterned structure.
10 . The method of claim 8 , wherein the dry etching process includes applying at least one of an oxygen-containing gas, a fluorine-containing gas, a chlorine-containing gas, or a bromine-containing gas on the patterned structure.
11 . A method for making a semiconductor device, comprising:
forming a first source/drain structure connected to a first fin and a second source/drain structure connected to a second fin, the first fin and second fin both extending in a first lateral direction, the first source/drain structure and second source/drain structure separated from each other in a second lateral direction perpendicular to the first lateral direction;
overlaying the first source/drain structure and the second source/drain structure with an interlayer dielectric;
forming a patterned structure over the interlayer dielectric, the patterned structure extending in the first lateral direction and having a vertical projection interposed between the first and second source/drain structures along the second lateral direction;
trimming the patterned structure to reduce a width of the patterned structure that extends along the second lateral direction, thereby increasing a dimension of interconnect structures coupled to the first source/drain structure and the second source/drain structure, respectively; and
exposing, based on the patterned structure having the reduced width, the first source/drain structure and the second source/drain structure by forming a first contact hole and a second contact hole, respectively; prior to the step of trimming the patterned structure, further comprising: depositing at least one imaging layer over the interlayer dielectric; and forming a trench in the at least one imaging layer that extends along the second lateral direction and exposes a central portion of the patterned structure.
12 . The method of claim 11 , wherein the step of trimming the patterned structure further comprises etching the central portion of the patterned structure through the trench, while clamping end portions of the patterned structure with the at least one imaging layer.
13 . The method of claim 11 , further comprising depositing a metal material over at least the exposed first source/drain structure and the exposed second source/drain structure to form a first interconnect structure and a second interconnect structure that electrically connect to the first and second source/drain structures, respectively.
14 . The method of claim 11 , wherein an amount of the reduced width is at least about 1 nanometer (nm).
15 . The method of claim 11 , subsequently to the step of trimming the patterned structure, further comprising:
depositing at least one imaging layer over the interlayer dielectric; and
forming a trench in the at least one imaging layer that extends along the second lateral direction and exposes a central portion of the patterned structure.
16 . The method of claim 11 , wherein the step of trimming the patterned structure further comprise performing at least one of a dry etching process or a wet etching process.
17 . A method for making a semiconductor device, comprising:
forming an interlayer dielectric to overlay a first source/drain structure coupled to a first fin extending in a first lateral direction and a second source/drain structure coupled to a second fin extending in the first lateral direction, wherein the first source/drain structure and the second source/drain structure are separated from each other along a second lateral direction perpendicular to the first lateral direction;
forming a patterned structure over the interlayer dielectric, wherein a vertical projection of the patterned structure is located between the first and second source/drain structures along the second lateral direction;
patterning an imaging layer over the interlayer dielectric to clamp end portions of the patterned structure and expose a central portion of the patterned structure;
reducing a width of the patterned structure that extends along the second lateral direction; and
etching the interlayer dielectric to form contact holes that expose the first source/drain structure and the second source/drain structure, respectively, based on the patterned structure having the reduced width.
18 . The method of claim 17 , wherein the step of reducing a width of the patterned structure further comprise performing at least one of a dry etching process or a wet etching process.