Granted Patent B2

US 12,740,101 · App. 18/081,332 · Granted Sep 15, 2026

Inventors: JungWook Lim (Daejeon, KR); Jieun Kim (Daejeon, KR)

Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE

H10D30/691G06N3/065G11C11/5671H10D30/6755

Abstract

Claims (48)

1 . A synaptic element which performs a multi-level logic operation, the synaptic element comprising:

a gate electrode to which a gate voltage pulse is applied;

a first electrode;

a second electrode; and

a multilayer tunnel insulating film in contact with each of the gate electrode, the first electrode, and the second electrode, and disposed such that the gate electrode is spaced apart from the first electrode and the second electrode, and

wherein the synaptic element generates a tunneling current flowing from the first electrode to the gate electrode through the multilayer tunnel insulating film based on the gate voltage pulse,

wherein the synaptic element operates in one of a turn-on mode, a turn-off mode, and an intermediate mode different from the turn-on mode and the turn-off mode based on the tunneling current, and

wherein the synaptic element is trained to generate a drain current in each of the turn-on mode, the turn-off mode, and the intermediate mode.

2 . The synaptic element of claim 1 , wherein a drain voltage is applied to the first electrode, and

wherein a magnitude of the drain current generated based on the gate voltage pulse varies depending on a level of the drain voltage.

3 . The synaptic element of claim 2 , wherein the synaptic element generates a drain current having a first value when a first drain voltage is applied, and

wherein the synaptic element is trained to generate a drain current having a second value greater than the first value when a second drain voltage having a level greater than that of the first drain voltage is applied.

4 . The synaptic element of claim 1 , wherein the synaptic element is trained to generate a first drain current when a first gate voltage pulse is applied to the gate electrode, and

wherein, when the number of the first gate voltage pulses increases, the synaptic element is trained such that the first drain current increases linearly by a first value in proportion to an increase in the number of the first gate voltage pulses.

5 . The synaptic element of claim 4 , wherein the synaptic element is trained to generate a second drain current when a second gate voltage pulse different from the first gate voltage pulse is applied to the gate electrode, and

wherein, when the number of the second gate voltage pulses increases, the synaptic element is trained such that the second drain current decreases linearly by a second value in proportion to an increase in the number of the second gate voltage pulses.

6 . The synaptic element of claim 5 , wherein a polarity of the second gate voltage pulse is opposite to that of the first gate voltage pulse.

7 . The synaptic element of claim 5 , wherein an intensity of the second gate voltage pulse is the same as an intensity of the first gate voltage pulse, and

wherein the second value is the same as the first value.

8 . The synaptic element of claim 4 , wherein the synaptic element is trained to generate a third drain current when a third gate voltage pulse having a pulse intensity lower than that of the first gate voltage pulse is applied to the gate electrode, and

wherein, when the number of the third gate voltage pulses increases, the synaptic element is trained such that the third drain current linearly increases by a third value less than the first value in proportion to an increase in the number of the third gate voltage pulses.

9 . An electronic circuit comprising:

a synaptic element; and

a variable resistor, and

wherein the synaptic element includes:

a gate electrode connected to an input terminal;

a first electrode;

a second electrode connected to one end of the variable resistor and an output terminal; and

a multilayer tunnel insulating film in contact with each of the gate electrode, the first electrode, and the second electrode, and disposed such that the gate electrode is spaced apart from the first electrode and the second electrode, and

wherein the synaptic element generates a tunneling current flowing from the first electrode to the gate electrode through the multilayer tunnel insulating film based on a gate voltage pulse applied to the gate electrode through the input terminal,

wherein the synaptic element operates in one of a turn-on mode, a turn-off mode, and an intermediate mode different from the turn-on mode and the turn-off mode based on the tunneling current,

wherein the synaptic element is trained to generate a drain current in each of the turn-on mode, the turn-off mode, and the intermediate mode, and

wherein the synaptic element controls an output voltage output to the output terminal through the second electrode based on the drain current and a resistance value of the variable resistor.

10 . The electronic circuit of claim 9 , wherein a drain voltage is applied to the first electrode, and

wherein a magnitude of the drain current generated based on the gate voltage pulse varies depending on a level of the drain voltage.

11 . The electronic circuit of claim 10 , wherein the synaptic element generates a drain current having a first value when a first drain voltage is applied, and

wherein the synaptic element is trained to generate a drain current having a second value greater than the first value when a second drain voltage having a level greater than that of the first drain voltage is applied.

12 . The electronic circuit of claim 10 , wherein, when the resistance value of the variable resistor increases and a first drain voltage is applied to the first electrode, the synaptic element allows a first output voltage having a first intensity to be output to the output terminal, and

wherein, when the resistance value of the variable resistor increases and a second drain voltage having an intensity lower than that of the first drain voltage is applied to the first electrode, the synaptic element allows a second output voltage having a second intensity lower than the first intensity to be output to the output terminal.

13 . The electronic circuit of claim 9 , wherein the synaptic element is trained to generate a first drain current when a first gate voltage pulse is applied to the gate electrode, and

wherein, when the number of the first gate voltage pulses increases, the synaptic element is trained such that the first drain current increases linearly by a first value in proportion to an increase in the number of the first gate voltage pulses.

14 . The electronic circuit of claim 13 , wherein the synaptic element is trained to generate a second drain current when a second gate voltage pulse different from the first gate voltage pulse is applied to the gate electrode, and

wherein, when the number of the second gate voltage pulses increases, the synaptic element is trained such that the second drain current decreases linearly by a second value in proportion to an increase in the number of the second gate voltage pulses.

15 . The electronic circuit of claim 14 , wherein a polarity of the second gate voltage pulse is opposite to that of the first gate voltage pulse.

16 . The electronic circuit of claim 14 , wherein an intensity of the second gate voltage pulse is the same as an intensity of the first gate voltage pulse, and

wherein the second value is the same as the first value.

17 . The electronic circuit of claim 13 , wherein the synaptic element is trained to generate a third drain current when a third gate voltage pulse having a pulse intensity lower than that of the first gate voltage pulse is applied to the gate electrode, and

wherein, when the number of the third gate voltage pulses increases, the synaptic element is trained such that the third drain current linearly increases by a second value less than the first value in proportion to an increase in the number of the third gate voltage pulses.

Assignments (1)

Priority Claims (2)

Continuity (1)

References Cited (23)