Fabrication of a vertical fin field effect transistor with reduced dimensional variations
A method of forming a fin field effect transistor (finFET) having fin(s) with reduced dimensional variations, including forming a dummy fin trench within a perimeter of a fin pattern region on a substrate, forming a dummy fin fill in the dummy fin trench, forming a plurality of vertical fins within the perimeter of the fin pattern region, including border fins at the perimeter of the fin pattern region and interior fins located within the perimeter and inside the bounds of the border fins, wherein the border fins are formed from the dummy fin fill, and removing the border fins, wherein the border fins are dummy fins and the interior fins are active vertical fins.
1. A method of manufacturing a device structure, the method comprising:
forming first fins in a first fin pattern in a first fin pattern region;
forming second fins in a second fin pattern, different from the first fin pattern, in a second fin pattern region adjacent to the first fin pattern region;
forming a dummy fin in a pattern region gap between the first and second fin pattern regions, wherein:
the first fin pattern region comprises a first active fin comprising a first material; and
the dummy fin comprises a second material different from the first material; and
removing the dummy fin.
2. The method of claim 1 , wherein the second fin pattern region comprises a second active fin comprising the first material.
3. The method of claim 1 , wherein the method further comprises removing more than one dummy fin comprising the second material from the pattern region gap.
4. The method of claim 1 , wherein the dummy fin is a first dummy fin and the first dummy fin is removed from a first row or column of fins, the method further comprising
removing a second dummy fin comprising the second material from the pattern region gap, wherein the second dummy fin is removed from a second row or column of fins different to the first row or column of fins of the first dummy fin.
5. The method of claim 1 , wherein a static random access memory, SRAM, comprises the first fin pattern region, and a processing core comprises the second fin pattern region.
6. The method of claim 1 , wherein a static random access memory, SRAM, comprises the first fin pattern region, and a graphics processor comprises the second fin pattern region.
7. The method of claim 1 , wherein a processing core comprises the first fin pattern region, and an input-output controller comprises the second fin pattern region.
8. The method of claim 1 , wherein a graphic processor comprises the first fin pattern region, and an input-output controller comprises the second fin pattern region.
9. The method of claim 1 , wherein a processing core comprises the first fin pattern region, and a heat and/or processing control circuit comprises the second fin pattern region.
10. The method of claim 1 , wherein a graphic processor comprises the first fin pattern region, and a heat and/or processing control circuit comprises the second fin pattern region.
11. The method of claim 1 , wherein a processing core comprises the first fin pattern region, and a register comprises the second fin pattern region.
12. The method of claim 1 , wherein a processing core comprises the first fin pattern region, and a memory comprises the second fin pattern region.
13. The method of claim 1 , wherein a graphic processor comprises the first fin pattern region, and a register comprises the second fin pattern region.
14. The method of claim 1 , wherein a graphic processor comprises the first fin pattern region, and a memory comprises the second fin pattern region.
15. The method of claim 1 , wherein prior to forming the first fins, the second fins and the dummy fin, the method further comprises:
forming a trench in a semiconductor substrate; and
depositing a fill material in the trench, wherein the fill material comprises the second material.
16. The method of claim 15 , the method further comprising:
subsequent to depositing the fill material in the trench, planarizing a surface of the semiconductor substrate to form a coplanar upper surface comprising an upper surface of the fill material and upper surfaces of the first and second fin pattern regions.
17. The method of claim 15 , wherein the dummy fin is located within the trench.
18. The method of claim 1 , wherein the first material is silicon.
19. The method of claim 1 , wherein the second material is silicon-germanium.
20. The method of claim 1 , wherein the dummy fin comprises silicon-germanium and the first active fin is substantially free of silicon-germanium.