Semiconductor device and semiconductor memory cell including the same
A semiconductor device includes a substrate, a gate electrode on the substrate, a channel layer between the substrate and the gate electrode, a source electrode in contact with a first sidewall of the channel layer, and a drain electrode in contact with a second sidewall of the channel layer. The second sidewall is opposite to the first sidewall. The channel layer includes a first channel pattern in contact with one of the source electrode and the drain electrode, and a second channel pattern between the first channel pattern and the gate electrode. The first channel pattern and the second channel pattern includes oxide semiconductor materials different from each other. A portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.
1 . A semiconductor device, comprising:
a substrate;
a gate electrode on the substrate;
a channel layer between the substrate and the gate electrode;
a source electrode in contact with a first sidewall of the channel layer; and
a drain electrode in contact with a second sidewall of the channel layer, the second sidewall being opposite to the first sidewall,
wherein the channel layer includes:
a first channel pattern that defines the first sidewall of the channel layer and the second sidewall of the channel layer, and
a second channel pattern between the first channel pattern and the gate electrode, the first channel pattern covering a first sidewall of the second channel pattern, a second sidewall of the second channel pattern opposite the first sidewall of the second channel pattern, and a bottom surface of the second channel pattern,
wherein the first channel pattern is formed of a first oxide semiconductor material, and the second channel pattern is formed of a second oxide semiconductor material different than the first oxide semiconductor material, and
wherein a portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.
2 . The semiconductor device as claimed in claim 1 , wherein the channel layer includes a compound of oxygen (O) and at least two metals selected from zinc (Zn), indium (In), gallium (Ga), and tin (Sn).
3 . The semiconductor device as claimed in claim 1 , wherein:
the first channel pattern includes a crystalline oxide semiconductor material, and
the second channel pattern includes an amorphous oxide semiconductor material.
4 . The semiconductor device as claimed in claim 1 , wherein a contact resistance of the first channel pattern is less than a contact resistance of the second channel pattern.
5 . The semiconductor device as claimed in claim 1 , wherein a mobility of the first channel pattern is less than a mobility of the second channel pattern.
6 . The semiconductor device as claimed in claim 1 , wherein the portion of the source electrode and the portion of the drain electrode vertically overlap the portion of the gate electrode.
7 . The semiconductor device as claimed in claim 1 , wherein:
the source electrode and the drain electrode are spaced apart from each other in a first direction parallel to a top surface of the substrate,
the gate electrode extends in a second direction that intersects the first direction and is parallel to the top surface of the substrate,
the source electrode includes:
a first source pattern in contact with the channel layer, and
a second source pattern on the first source pattern, the second source pattern overlapping in the first direction with a part of the gate electrode,
the drain electrode includes:
a first drain pattern in contact with the channel layer, and
a second drain pattern on the first drain pattern, the second drain pattern overlapping in the first direction with the part of the gate electrode,
a length in the first direction of the second source pattern is less than a length in the first direction of the first source pattern, and
a length in the first direction of the second drain pattern is less than a length in the first direction of the first drain pattern.
8 . The semiconductor device as claimed in claim 1 , wherein the second channel pattern is formed of amorphous indium-gallium-zinc oxide, In 2 O 3 , or indium-tungsten oxide and has a constitution ratio of indium greater than 1 to 3.
9 . A semiconductor device, comprising:
a substrate;
a gate electrode on the substrate;
a channel layer between the substrate and the gate electrode;
a source electrode in contact with a first sidewall of the channel layer; and
a drain electrode in contact with a second sidewall of the channel layer, the second sidewall being opposite to the first sidewall,
wherein the source electrode and the drain electrode are spaced apart from each other in a first direction parallel to a top surface of the substrate,
wherein the gate electrode extends in a second direction that intersects the first direction and is parallel to the top surface of the substrate,
wherein the channel layer includes:
a first channel pattern that defines the first sidewall of the channel layer and the second sidewall of the channel layer, and
a second channel pattern between the first channel pattern and the gate electrode, the first channel pattern covering a first sidewall of the second channel pattern, a second sidewall of the second channel pattern opposite the first sidewall of the second channel pattern, and a bottom surface of the second channel pattern,
wherein the first channel pattern is formed of a first oxide semiconductor material, and the second channel pattern is formed of a second oxide semiconductor material that is different than the first oxide semiconductor material, and
wherein a portion of the source electrode and a portion of the drain electrode overlap in a third direction with a portion of the gate electrode, the third direction being perpendicular to the top surface of the substrate.
10 . The semiconductor device as claimed in claim 9 , wherein:
the first channel pattern includes c-axis aligned crystal indium-gallium-zinc oxide (CAAC-IGZO) or indium-tin oxide (ITO), and
the second channel pattern includes indium-gallium-zinc oxide (IGZO), In 2 O 3 , or indium-tungsten oxide (IWO).
11 . A semiconductor memory cell, comprising:
a substrate;
a semiconductor device on the substrate;
a landing pad on the semiconductor device; and
a capacitor that includes bottom electrodes, a top electrode, and a dielectric layer between the bottom electrodes and the top electrode, the capacitor being connected through the landing pad to the semiconductor device, wherein the semiconductor device includes:
a gate electrode on the substrate,
a channel layer between the substrate and the gate electrode,
a source electrode in contact with a first sidewall of the channel layer, and
a drain electrode in contact with a second sidewall of the channel layer, the second sidewall being opposite to the first sidewall,
wherein the channel layer of the semiconductor device includes:
a first channel pattern that defines the first sidewall of the channel layer and the second sidewall of the channel layer, the first channel pattern including a crystalline oxide semiconductor material, and
a second channel pattern between the first channel pattern and the gate electrode, the second channel pattern including an amorphous oxide semiconductor material, the first channel pattern covering a first sidewall of the second channel pattern, a second sidewall of the second channel pattern opposite the first sidewall of the second channel pattern, and a bottom surface of the second channel pattern,
wherein the first channel pattern is formed of a first oxide semiconductor material, and the second channel pattern is formed of a second oxide semiconductor material that is different than the first oxide semiconductor material, and
wherein a portion of the source electrode and a portion of the drain electrode overlap a portion of the gate electrode.
12 . The semiconductor memory cell as claimed in claim 11 , further comprising a bit line on the source electrode,
wherein the drain electrode is connected through the landing pad to the capacitor.