Semiconductor apparatus
A semiconductor apparatus includes a bit line extending in a first horizontal direction on a substrate; a channel layer on the bit line, the channel layer extending in a vertical direction, including a first oxide semiconductor material that includes indium, and having a first side wall and a second side wall; a word line on the first side wall of the channel layer; a contact forming region on a top surface and an upper portion of the second side wall of the channel layer, the contact forming region including a second oxide semiconductor material that includes indium and having a resistivity lower than a resistivity of the channel layer; a contact layer on the contact forming region; and a capacitor structure on a top surface of the contact layer.
1 . A semiconductor apparatus, comprising:
a bit line extending in a first horizontal direction on a substrate;
a channel layer on the bit line, the channel layer extending in a vertical direction, including a first oxide semiconductor material that includes indium, and having a first side wall and a second side wall;
a word line on the first side wall of the channel layer;
a contact forming region on a top surface and an upper portion of the second side wall of the channel layer, the contact forming region including a second oxide semiconductor material that includes indium and having a resistivity lower than a resistivity of the channel layer;
a contact layer on the contact forming region; and
a capacitor structure on a top surface of the contact layer.
2 . The semiconductor apparatus as claimed in claim 1 , wherein:
the first oxide semiconductor material includes InGaZnO x (IGZO), Sn-doped IGZO, W-doped IGZO, or InZnO x (IZO), and
the second oxide semiconductor material includes IGZO, Sn-doped IGZO, W-doped IGZO, or IZO.
3 . The semiconductor apparatus as claimed in claim 2 , wherein:
the channel layer has a first indium content, and
the contact forming region has a second indium content greater than the first indium content.
4 . The semiconductor apparatus as claimed in claim 2 , wherein:
the channel layer has a first zinc content, and
the contact forming region has a second zinc content less than the first zinc content.
5 . The semiconductor apparatus as claimed in claim 1 , wherein the contact forming region includes:
a horizontal extending portion on the top surface of the second side wall of the channel layer, and
a vertical extending portion on the upper portion of the second side wall of the channel layer.
6 . The semiconductor apparatus as claimed in claim 5 , further comprising a mold layer surrounding the second side wall of the channel layer,
wherein the vertical extending portion and the horizontal extending portion of the contact forming region are at a higher vertical level than a top surface of the mold layer.
7 . The semiconductor apparatus as claimed in claim 6 , wherein:
a side wall of the vertical extending portion of the contact forming region is aligned with the second side wall of the channel layer, and
the side wall of the vertical extending portion is not surrounded by the mold layer.
8 . The semiconductor apparatus as claimed in claim 6 , wherein:
the contact layer covers a side wall of the vertical extending portion and a top surface of the horizontal extending portion of the contact forming region, and
the contact layer contacts the top surface of the mold layer.
9 . The semiconductor apparatus as claimed in claim 6 , wherein a side wall of the vertical extending portion of the contact forming region is recessed inwardly with respect to the second side wall of the channel layer.
10 . The semiconductor apparatus as claimed in claim 6 , wherein:
the horizontal extending portion of the contact forming region has a first height in the vertical direction,
the vertical extending portion of the contact forming region has a first width in the first horizontal direction, and
the first height ranges from 80% to 120% of the first width.
11 . A semiconductor apparatus, comprising:
a bit line extending in a first horizontal direction on a substrate;
a channel layer on the bit line, the channel layer extending in a vertical direction, including a first oxide semiconductor material that includes indium, and having a first side wall and a second side wall;
a word line on the first side wall of the channel layer;
a contact forming region on a top surface of the channel layer, the contact forming region including a second oxide semiconductor material that includes indium;
a contact layer on the contact forming region; and
a capacitor structure on the contact layer,
wherein:
the channel layer has a first indium content, and
the contact forming region has a second indium content greater than the first indium content.
12 . The semiconductor apparatus as claimed in claim 11 , wherein:
the first oxide semiconductor material includes InGaZnO x (IGZO), Sn-doped IGZO, W-doped IGZO, or InZnO x (IZO), and
the second oxide semiconductor material includes IGZO, Sn-doped IGZO, W-doped IGZO, or IZO.
13 . The semiconductor apparatus as claimed in claim 12 , wherein:
the channel layer has a first zinc content, and
the contact forming region has a second zinc content less than the first zinc content.
14 . The semiconductor apparatus as claimed in claim 11 , wherein the contact forming region includes:
a horizontal extending portion on the top surface of the channel layer, and
a vertical extending portion connected to the horizontal extending portion, the vertical extending portion being on an upper portion of the second side wall of the channel layer.
15 . The semiconductor apparatus as claimed in claim 14 , further comprising a mold layer surrounding the second side wall of the channel layer,
wherein:
a side wall of the vertical extending portion of the contact forming region is aligned with the second side wall of the channel layer, and
the side wall of the vertical extending portion does not contact the mold layer.
16 . The semiconductor apparatus as claimed in claim 15 , wherein:
the contact layer covers the side wall of the vertical extending portion and a top surface of the horizontal extending portion of the contact forming region, and
the contact layer contacts a top surface of the mold layer.
17 . The semiconductor apparatus as claimed in claim 14 , wherein:
the vertical extending portion of the contact forming region has a first width in the first horizontal direction,
the horizontal extending portion of the contact forming region has a first height in the vertical direction, and
the first height ranges from 80% to 120% of the first width.
18 . A semiconductor apparatus, comprising:
a bit line extending in a first horizontal direction on a substrate;
a mold layer covering the bit line on the substrate, the mold layer including a mold opening;
a channel layer on an inner wall of the mold opening, the channel layer extending in the first horizontal direction, including a first portion contacting a top surface of the bit line and a second portion extending in a vertical direction on the inner wall of the mold opening, and including a first oxide semiconductor material that includes indium;
a word line in the mold opening, the word line being on a first side wall of the second portion of the channel layer;
a contact forming region covering the channel layer, the contact forming region including a second oxide semiconductor material that includes indium and including a horizontal extending portion located on a top surface of the channel layer and a vertical extending portion located on an upper portion of a second side wall opposite to the first side wall of the second portion of the channel layer;
a contact layer covering the contact forming region; and
a capacitor structure on the contact layer,
wherein:
the channel layer has a first indium content, and
the contact forming region has a second indium content greater than the first indium content.
19 . The semiconductor apparatus as claimed in claim 18 , wherein:
a side wall of the vertical extending portion of the contact forming region is aligned with the second side wall of the channel layer, and
the side wall of the vertical extending portion does not contact the mold layer.
20 . The semiconductor apparatus as claimed in claim 18 , wherein the contact layer contacts a top surface of the mold layer.