IP Library › Granted Patent US 12,199,122
Granted Patent B2
US 12,199,122 · App. 18/105,005 · Granted Jan 14, 2025

Imaging device and electronic device

Inventors: Tatsuya Onuki (Kanagawa, JP); Kiyoshi Kato (Kanagawa, JP); Takanori Matsuzaki (Kanagawa, JP); Hajime Kimura (Kanagawa, JP); Shunpei Yamazaki (Tokyo, JP)
Assignee: Semiconductor Energy Laboratory Co., Ltd.
H01L27/14634H01L27/1207H01L27/1225H01L27/1255H01L29/78648H01L29/7869H04N25/771H04N25/772H10B12/00
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Quick Facts
Patent No.
US 12,199,122
App. No.
18/105,005
Granted
Jan 14, 2025
Kind
B2
Abstract

An imaging device which has a stacked-layer structure and can be manufactured easily is provided. The imaging device includes a signal processing circuit, a memory device, and an image sensor. The imaging device has a stacked-layer structure in which the memory device is provided above the signal processing circuit, and the image sensor is provided above the memory device. The signal processing circuit includes a transistor formed on a first semiconductor substrate, the memory device includes a transistor including a metal oxide in a channel formation region, and the image sensor includes a transistor formed on a second semiconductor substrate.

Claims (45)

1. A semiconductor device comprising:

a first layer comprising a plurality of circuits;

a second layer above the first layer, the second layer comprising a plurality of memory cells electrically connected to the plurality of circuits; and

a third layer above the second layer, the third layer comprises an image sensor electrically connected to the plurality of circuits,

wherein one of the plurality of circuits comprises a first transistor,

wherein the first transistor comprises a first crystalline semiconductor material in a channel formation region,

wherein each of the plurality of memory cells comprises a second transistor,

wherein the second transistor comprises a metal oxide in a channel formation region and a gate and a back gate with the channel formation region provided therebetween,

wherein the image sensor comprises a plurality of pixels each comprising a third transistor and a photodiode,

wherein the third transistor comprises a second crystalline semiconductor material in a channel formation region, and

wherein a semiconductor region of the photodiode comprises the second crystalline semiconductor material.

2. The semiconductor device according to claim 1 ,

wherein at least one of the first crystalline semiconductor material and the second crystalline semiconductor material is single crystal silicon.

3. The semiconductor device according to claim 1 ,

wherein the channel formation region of the first transistor is provided in a first semiconductor substrate, and

wherein the channel formation region of the third transistor is provided in a second semiconductor substrate.

4. The semiconductor device according to claim 1 ,

wherein the metal oxide comprises at least indium and zinc.

5. The semiconductor device according to claim 1 ,

wherein the plurality of pixels are stacked over the plurality of the memory cells.

6. The semiconductor device according to claim 1 ,

wherein at least part of the third transistor overlaps with the second transistor and the first transistor.

7. A semiconductor device comprising:

a first layer comprising a plurality of circuits;

a second layer above the first layer, the second layer comprising a plurality of memory cells electrically connected to the plurality of circuits; and

a third layer above the second layer, the third layer comprises an image sensor electrically connected to the plurality of circuits,

wherein one of the plurality of circuits comprises a first transistor,

wherein the first transistor comprises a first crystalline semiconductor material in a channel formation region,

wherein each of the plurality of memory cells comprises a second transistor and a capacitor,

wherein the second transistor comprises a metal oxide in a channel formation region, a source, a drain, and a gate and a back gate with the channel formation region provided therebetween,

wherein a first electrode of the capacitor is electrically connected to one of the source and the drain of the second transistor,

wherein the image sensor comprises a plurality of pixels each comprising a third transistor and a photodiode,

wherein the third transistor comprises a second crystalline semiconductor material in a channel formation region, and

wherein a semiconductor region of the photodiode comprises the second crystalline semiconductor material.

8. The semiconductor device according to claim 7 ,

wherein at least one of the first crystalline semiconductor material and the second crystalline semiconductor material is single crystal silicon.

9. The semiconductor device according to claim 7 ,

wherein the channel formation region of the first transistor is provided in a first semiconductor substrate, and

wherein the channel formation region of the third transistor is provided in a second semiconductor substrate.

10. The semiconductor device according to claim 7 ,

wherein the metal oxide comprises at least indium and zinc.

11. The semiconductor device according to claim 7 ,

wherein the plurality of pixels are stacked over the plurality of the memory cells.

12. The semiconductor device according to claim 7 ,

wherein at least part of the third transistor overlaps with the second transistor, the capacitor, and the first transistor.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 2, 2023
From: ONUKI, TATSUYA; KATO, KIYOSHI; MATSUZAKI, TAKANORI; KIMURA, HAJIME; YAMAZAKI, SHUNPEI
To: SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
Reel/Frame 062574/0885 →
Priority Claims (2)
JP 2017-225285 · Nov 23, 2017 · national
JP 2018-030881 · Feb 23, 2018 · national
Continuity (2)
Continuation 16763024
Related Publication 20230230994A1 · Jul 20, 2023
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Cited By (1)
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