3D memory devices and structures with control circuits
A semiconductor device, the device including: a first level including control circuits, where the control circuits include a plurality of first transistors and a plurality of metal layers; and a memory level disposed on top of the first level, where the memory level includes an array of memory cells, where each of the memory cells includes at least one second transistor, where the control circuits control access to the array of memory cells, where the first level is bonded to the memory level, where the bonded includes oxide to oxide bonding regions and a plurality of metal to metal bonding regions, and where at least a portion of the array of memory cells is disposed directly above at least one of the plurality of metal to metal bonding regions.
1. A semiconductor device, the device comprising:
a first level comprising control circuits,
wherein said control circuits comprise a plurality of first transistors and a plurality of metal layers;
a memory level disposed on top of said first level,
wherein said memory level comprises an array of memory cells,
wherein each of said memory cells comprises at least one second transistor,
wherein said control circuits control access to said array of memory cells,
wherein said first level is bonded to said memory level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein at least a portion of said array of memory cells is disposed directly above at least one of said plurality of metal to metal bonding regions,
wherein said memory level comprises at least one redundancy memory array, and
wherein said control circuits control access is switchable to access or not access said at least one redundancy memory array.
2. The device according to claim 1 ,
wherein said memory level comprises a single crystal silicon layer having a thickness of less than 30 microns and greater than 0.1 microns.
3. The device according to claim 1 ,
wherein said array of memory cells comprises DRAM memory.
4. The device according to claim 1 ,
wherein said array of memory cells comprises 3D NAND memory.
5. The device according to claim 1 ,
wherein said memory level comprises a plurality of memory layers.
6. The device according to claim 1 ,
wherein said array of memory cells comprises at least four sub-arrays, and
wherein said control circuits independently control access to each of said sub-arrays.
7. The device according to claim 1 ,
wherein said array of memory cells comprises a plurality of word-lines (“WL”), and
wherein at least one of said plurality of word-lines is directly connected to at least one of said plurality metal to metal bonding regions.
8. A semiconductor device, the device comprising:
a first level comprising control circuits,
wherein said control circuits comprise a plurality of first transistors and a plurality of metal layers;
a memory level disposed on top of said first level,
wherein said memory level comprises an array of memory cells,
wherein each of said memory cells comprises at least one second transistor,
wherein said control circuits control access to said array of memory cells,
wherein said first level is bonded to said memory level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said array of memory cells comprises a plurality of memory control-lines, and
wherein at least one of said plurality of memory control-lines is directly connected to at least one of said metal to metal bonding regions: and
a redundancy memory array, and
wherein said memory control-lines are connectable to control said redundancy memory array.
9. The device according to claim 8 ,
wherein said first level comprises a single crystal silicon layer having a thickness of less than 30 microns and greater than 0.1 microns.
10. The device according to claim 8 ,
wherein said array of memory cells comprises DRAM memory.
11. The device according to claim 8 ,
wherein said array of memory cells comprises 3D NAND memory.
12. The device according to claim 8 ,
wherein said first memory level comprises a plurality of memory layers.
13. The device according to claim 8 ,
wherein said array of memory cells comprises at least four sub-arrays, and
wherein said control circuits independently control each of said sub-arrays.
14. The device according to claim 8 ,
wherein at least one of said memory cells is disposed directly above at least one of said metal to metal bonding regions.
15. A semiconductor device, the device comprising:
a first level comprising control circuits,
wherein said control circuits comprise a plurality of first transistors and a plurality of metal layers; and
a memory level disposed on top of said first level,
wherein said memory level comprises an array of memory cells,
wherein each of said memory cells comprises at least one second transistor,
wherein said control circuits control access to said array of memory cells,
wherein said first level is bonded to said memory level,
wherein said bonded comprises oxide to oxide bonding regions and a plurality of metal to metal bonding regions,
wherein said array of memory cells comprises at least four sub-arrays,
wherein said control circuits independently control access to each of said sub-arrays, and
wherein said first level has been processed by a more advanced node than a node used for said memory level.
16. The device according to claim 15 ,
wherein said memory array comprises a plurality of word-lines (“WL”), and
wherein at least one of said word-lines is directly connected to at least one of said metal to metal bonding regions.
17. The device according to claim 15 ,
wherein said array of memory cells comprises DRAM memory.
18. The device according to claim 15 ,
wherein said array of memory cells comprises 3D NAND memory.
19. The device according to claim 15 ,
wherein said memory level comprises a plurality of memory layers.
20. The device according to claim 15 ,
wherein at least one of said memory cells is disposed directly above at least one of said metal to metal bonding regions.