Semiconductor device and method of fabricating the same
A semiconductor device comprising a substrate, lower electrodes vertically extended on the substrate and horizontally spaced apart from each other, a conductive pattern provided on the substrate to conformally cover the lower electrodes, supporting patterns provided to penetrate the conductive pattern and connected to portions of side surfaces of the lower electrodes, and conductive islands disposed on surfaces of the supporting patterns. The conductive islands may be distributed on the surfaces of the supporting patterns to be spaced apart from each other, and the conductive pattern may be spaced apart from and electrically disconnected from the conductive islands.
1 . A method of fabricating a semiconductor device, comprising:
forming an insulating layer on a substrate;
forming lower electrode contacts on the substrate to penetrate the insulating layer;
alternatingly stacking sacrificial layers and supporting layers on the insulating layer to form a stack;
forming lower electrodes to penetrate the stack and to be in contact with the lower electrode contacts;
patterning the supporting layers to form supporting patterns;
removing the sacrificial layers to expose the lower electrodes;
performing a deposition process, in which a metal material is used, on the lower electrodes and the supporting patterns to form a conductive pattern on the lower electrodes;
forming a dielectric layer to cover the supporting patterns and the conductive pattern; and
forming an upper electrode to cover the dielectric layer,
wherein the conductive pattern is formed to cover top surfaces and side surfaces of the lower electrodes, which are exposed by the supporting patterns, and to expose the supporting patterns, and
wherein in the deposition process, a first deposition rate of the metal material deposited on the lower electrodes is faster than a second deposition rate of the metal material deposited on the supporting patterns.
2 . The method of claim 1 ,
wherein the supporting patterns contain carbon (C), and
wherein a concentration of carbon (C) in the supporting patterns is higher than a concentration of carbon (C) in the lower electrodes.
3 . The method of claim 1 , wherein the deposition process is performed at a temperature of 250° C. to 700° C.
4 . The method of claim 1 , wherein, during the deposition process, the metal material is deposited on the supporting patterns to form conductive islands, which are scattered on the surfaces of the supporting patterns and are spaced apart from each other.
5 . The method of claim 1 , wherein the metal material comprises niobium (Nb), tantalum (Ta), tin (Sn), molybdenum (Mo), titanium (Ti), indium (In), nickel (Ni), cobalt (Co), tungsten (W), or ruthenium (Ru).
6 . The method of claim 1 , wherein the dielectric layer is spaced apart from the lower electrodes with the conductive pattern interposed therebetween.
7 . A method of fabricating a semiconductor device, comprising:
stacking a sacrificial layer and a supporting layer on a substrate;
forming lower electrodes to penetrate the supporting layer and the sacrificial layer and to be in contact with the substrate;
patterning the supporting layer to form a supporting pattern;
removing the sacrificial layer to expose side surfaces of the lower electrodes, which are not in contact with the supporting pattern; and
performing a deposition process, in which a metal material is used, on the lower electrodes and the supporting pattern to form a conductive pattern on top surfaces of the lower electrodes and on the side surfaces of the lower electrodes, which are not in contact with the supporting pattern,
wherein the conductive pattern is formed to expose a surface of the supporting pattern,
wherein the deposition process comprises repeating a cycle, and
wherein a number of the cycles, which are repeated to deposit a single atomic layer of the metal material on the lower electrode, is less than a number of the cycles, which are repeated to deposit a single atomic layer of the metal material on the supporting pattern.
8 . The method of claim 7 , wherein the cycle comprises:
supplying a gas containing a precursor material to adsorb the precursor material on the lower electrodes and the supporting pattern;
purging the gas containing a portion of the precursor material, which is not adsorbed on the lower electrodes and the supporting pattern;
supplying a reaction gas, which is used for reaction with the precursor material; and
purging a portion of the reaction gas, which does not react with the precursor material.
9 . The method of claim 7 , wherein the deposition process comprises:
forming islands on the surface of the lower electrodes or the surface of the supporting pattern; and
enlarging the islands to form a single atomic layer of the metal material.
10 . The method of claim 9 , wherein the deposition process is performed to form a layer, which contains the metal material and has at least a thickness of a single atomic layer, on the lower electrode, and to form the islands, which contain the metal material, on the supporting pattern.
11 . The method of claim 7 , wherein the supporting pattern contains carbon (C).
12 . The method of claim 7 , wherein the deposition process is performed at a temperature of 250° C. to 700° C.
13 . The method of claim 7 , wherein the conductive pattern is selectively deposited on the top and side surfaces of the lower electrodes, which are not in contact with the supporting pattern.
14 . The method of claim 7 , further comprising:
forming a dielectric layer on the supporting pattern and the conductive pattern; and
forming an upper electrode on the dielectric layer.