Semiconductor device having deep trench structure and method of manufacturing thereof
A semiconductor device includes etch stop films formed on the first gate electrode, the first source region, the first drain region, and the shallow trench isolation regions, respectively. First interlayer insulating films are formed on the etch stop film, respectively. Deep trenches are formed in the substrate between adjacent ones of the first interlayer insulating films to overlap the shallow trench isolation regions. Sidewall insulating films are formed in the deep trenches, respectively. A gap-fill insulating film is formed on the sidewall insulating film. A second interlayer insulating film is formed on the gap-fill insulating film. A top surface of the second interlayer insulating film is substantially planar and a bottom surface of the second interlayer insulating film is undulating.
1. A method of manufacturing a semiconductor device, the method comprising:
providing an active region and a shallow trench region on a substrate;
forming a gate electrode on the active region;
forming a first interlayer insulating film on the gate electrode;
forming a deep trench in the substrate;
forming a gap-fill insulating film on the gate electrode and sidewalls of the deep trench to fill the deep trench and seal an opening of the deep trench;
forming a second interlayer insulating film on the gap-fill insulating film, wherein the second interlayer insulating film comprises:
a convex region overlapping the gate electrode; and
a concave region overlapping the deep trench;
selectively removing the convex region of the second interlayer insulating film to reduce a thickness of the second interlayer insulating film overlapping the gate electrode;
forming a third interlayer insulating film on the second interlayer insulating film;
forming a contact plug connected to the active region; and
forming a metal wiring on the contact plug.
2. The method of claim 1 , wherein the selectively removing of the convex region comprises:
forming a blocking pattern on the concave region overlapping the deep trench;
performing an etch-back process on the convex region overlapping the gate electrode; and
removing the blocking pattern.
3. The method of claim 1 , further comprising:
performing, after selectively removing the convex region, a chemical mechanical polishing (CMP) of the second interlayer insulating film to form a planarized interlayer insulating film.
4. The method of claim 1 , further comprising:
forming an etch stop film on the gate electrode,
wherein the etch stop film and the first interlayer insulating film form a hard mask layer.
5. The method of claim 4 , wherein the contact plug is formed through the etch stop film, the first interlayer insulating film, the gap-fill insulating film, the second interlayer insulating film, and the third interlayer insulating film.
6. The method of claim 1 , wherein the deep trench comprises an air gap formed by sealing the opening of the deep trench with the gap-fill insulating film and surrounded by the gap-fill insulating film.
7. The method of claim 1 , further comprising:
forming a sidewall insulating film on the sidewalls of the deep trench,
wherein the gap-fill insulating film is in direct contact with the sidewall insulating film.
8. A method of manufacturing a semiconductor device, the method comprising:
providing an active region and an isolation region on a substrate;
forming a gate electrode on the active region;
forming a first interlayer insulating film on the gate electrode;
forming a deep trench through the isolation region on the substrate;
forming a gap-fill insulating film on the gate electrode and sidewalls of the deep trench to fill the deep trench and seal an opening of the deep trench;
forming a second interlayer insulating film on the gap-fill insulating film, the second interlayer insulating film comprising a convex region overlapping the gate electrode and a concave region overlapping the deep trench;
performing an etch-back process on the second interlayer insulating film to selectively remove the convex region of the second interlayer insulating film overlapping the gate electrode;
forming a contact plug connected to the active region; and
forming a metal wiring on the contact plug.
9. The method of claim 8 , wherein the performing of the etch-back process on the second interlayer insulating film comprises:
forming a blocking pattern on the concave region of the second interlayer insulating film overlapping the deep trench; and
performing the etch-back process on the convex region of the second interlayer insulating film using the blocking pattern as a mask pattern; and
removing the blocking pattern.
10. The method of claim 8 , further comprising:
performing a planarization process on the second interlayer insulating film after the performing of the etch-back process on the second interlayer insulating film.
11. The method of claim 8 , further comprising:
depositing a third interlayer insulating film on the second interlayer insulating film,
wherein the contact plug is formed through the first interlayer insulating film, the gap-fill insulating film, the second interlayer insulating film, and the third interlayer cap-insulating film.
12. The method of claim 8 , further comprising:
forming a first buried layer on the substrate;
forming a second buried layer on the first buried layer, the first buried layer and the second buried layer having different conductivity types;
forming a drift region and a body region, respectively, on the second buried layer, the drift region and the body region having different conductivity types; and
forming a source region and a drain region in the body region and the drift region, respectively.
13. A method of manufacturing a semiconductor device, the method comprising:
providing an active region and an isolation region on a substrate;
forming a gate electrode on the active region;
forming a first interlayer insulating film on the gate electrode;
forming a deep trench through the isolation region on the substrate;
forming a gap-fill insulating film on the gate electrode and sidewalls of the deep trench to fill the deep trench and seal an opening of the deep trench;
forming a second interlayer insulating film on the gap-fill insulating film, the second interlayer insulation film comprising a convex region overlapping the gate electrode and a concave region overlapping the deep trench;
selectively removing the convex region of the second interlayer insulating film by forming a blocking pattern on the concave region of the second interlayer insulating film and performing an etch-back process on the convex region using the blocking pattern as a mask pattern, thereby reducing a thickness of the second interlayer insulating film;
performing a planarization process on the second interlayer insulating film;
forming a contact plug connected to the active region; and
forming a metal wiring on the contact plug.
14. The method of claim 13 , wherein the performing of the planarization process on the second interlayer insulating film comprises:
performing a chemical mechanical polishing (CMP) of the second interlayer insulating film to form a planarized interlayer insulating film.
15. The method of claim 14 , wherein the selectively removing of the convex region first of the second interlayer insulating film overlapping the gate electrode further comprises:
removing the blocking pattern before performing the planarization process.
16. The method of claim 13 , further comprising:
forming a third interlayer insulating film on the planarized second interlayer insulating film,
wherein the contact plug is formed through the first interlayer insulating film, the gap-fill insulating film, the second interlayer insulating film, and the third interlayer insulating film.