IP Library Granted Patent US 12,418,989
Granted Patent B2
US 12,418,989 · App. 18/123,881 · Granted Sep 16, 2025

Packaged circuit structure

Inventors: Chun-Chieh Huang (Taoyuan, TW); Chin-Ming Liu (Taoyuan, TW)
Assignees: Leading Interconnect Semiconductor Technology Qinhuangdao Co., Ltd.; Leading Interconnect Semiconductor Technology (ShenZhen) Co., Ltd.
H05K1/186H05K3/284H05K3/4697H05K1/183H05K2201/10553H05K2203/308
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Quick Facts
Patent No.
US 12,418,989
App. No.
18/123,881
Granted
Sep 16, 2025
Kind
B2
Abstract

A package circuit structure includes a multilayer circuit board, an electronic component, and an insulating layer. The multilayer circuit board includes a metal portion and an opening. The opening is extending from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side. A bottom of the opening is sealed by the metal portion. The electronic component is received in the opening and adhered to the metal portion. The electronic component is electrically connected to the multilayer circuit board and encapsulated in the opening by the insulating layer. A method for manufacturing the package circuit structure is also provided.

Claims (13)

1. A package circuit structure comprising:

a multilayer circuit board, wherein the multilayer circuit board comprises a metal portion and an opening, the opening extends from a first side of the multilayer circuit board toward the second side of the multilayer circuit board facing the first side, a bottom of the opening is sealed by the metal portion;

an electronic component, wherein the electronic component is received in the opening and adhered to the metal portion, the electronic component is electrically connected to the multilayer circuit board; and

an insulating layer, wherein the insulating layer encapsulates the electronic component in the opening;

wherein the multilayer circuit board further comprises a first wiring layer, a second wiring layer, a third wiring layer, and a fourth wiring layer stacked in that order; the second wiring layer comprises the metal portion, the third wiring layer comprises a first gap corresponding to the metal portion, the fourth wiring comprises a second gap corresponding to the metal portion;

wherein a size of the first gap is greater than a size of the metal portion, and/or, a size of the second gap is greater than a size of the metal portion.

2. The package circuit structure of claim 1 , wherein a width of the opening decreases from the first side of the multilayer circuit board toward the second side of the multilayer circuit board.

3. The package circuit structure of claim 1 , wherein a width of the opening is same from the first side toward the second side.

4. The package circuit structure of claim 1 , wherein the insulating layer is formed on the first side of the multilayer circuit board, fills in the opening, and covers the electronic component.

5. The package circuit structure of claim 1 , wherein the multilayer circuit board further comprises two solder masks respectively formed on the first wiring layer and the fourth wiring layer, the opening is exposed from one of the two solder masks on the fourth wiring layer.

6. The package circuit structure of claim 5 , wherein one of the two solder masks on the fourth wiring layer comprises a third gap corresponding to the metal portion.

7. The package circuit structure of claim 6 , wherein a size of the third gap is greater than a size of the metal portion.

8. The package circuit structure of claim 6 , wherein a plurality of connecting pads is formed on the second side of the multilayer circuit board, and a solder ball is formed on each of the plurality of connecting pads.

Assignments (2)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jan 22, 2024
From: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
To: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
Reel/Frame 066191/0851 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 20, 2023
From: HUANG, CHUN-CHIEH; LIU, CHIN-MING
To: LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY QINHUANGDAO CO., LTD.; QI DING TECHNOLOGY QINHUANGDAO CO., LTD.; LEADING INTERCONNECT SEMICONDUCTOR TECHNOLOGY (SHENZHEN) CO.,LTD.
Reel/Frame 063038/0447 →
Priority Claims (1)
CN 202110097582.X · Jan 25, 2021 · national
Continuity (2)
Division 17218556 · Mar 31, 2021
Related Publication 20230232537A1 · Jul 20, 2023
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