Semiconductor storage device and manufacturing method thereof
A semiconductor storage device includes a first layer including a first surface and a second surface located opposite to the first surface. The first layer includes a first memory cell array and a first wire layer, the first memory cell array being provided between the first surface and the second surface and including a plurality of first memory cells, and the first wire layer facing the first surface and being electrically connected to the first memory cells. A second layer includes a third surface and a fourth surface located opposite to the third surface. The second layer includes a second memory cell array provided between the third surface and the fourth surface to be electrically connected to the first wire layer and including a plurality of second memory cells. The first layer and the second layer are joined together on the first surface and the third surface.
1 . A semiconductor storage device comprising:
a first layer including a first surface and a second surface located opposite to the first surface, the first layer including a first memory cell array and a first wire layer, the first memory cell array being provided between the first surface and the second surface and including a plurality of first memory cells, and the first wire layer facing the first surface and being electrically connected to the first memory cells;
a second layer including a third surface and a fourth surface located opposite to the third surface, the second layer including a second memory cell array provided between the third surface and the fourth surface to be electrically connected to the first wire layer and including a plurality of second memory cells, the second layer further including a first pad facing the third surface and electrically connected to the second memory cells;
a third layer including a fifth surface and a sixth surface located opposite to the fifth surface, the third layer including a CMOS circuit provided between the fifth surface and the sixth surface to be electrically connected to the first and second memory cells and the first wire layer;
a fourth layer including a seventh surface and an eighth surface located opposite to the seventh surface, the fourth layer including a third wire layer to be electrically connected to the first and second memory cells, the first wire layer and the CMOS circuit;
a contact plug penetrating the fourth layer and the second layer and electrically connected to the first wire layer; and
a second pad electrically connected to the contact plug on the seventh surface, wherein
the first layer and the second layer are joined together on the first surface and the third surface,
the first layer and the third layer are joined together on the second surface and the fifth surface,
the second layer and the fourth layer are joined together via the fourth surface and the eighth surface,
the first wire layer and the first pad are directly joined together via the first surface and the third surface, and
the first wire layer is set to a predetermined source voltage through the second pad and the contact plug.
2 . The device of claim 1 , wherein
the first wire layer comprises a source layer.
3 . The device of claim 1 , wherein
the first layer further includes a CMOS (Complementary Metal Oxide Semiconductor) circuit provided between the first memory cell array and the second surface, and
the first memory cells and the second memory cells are electrically connected to the CMOS circuit.
4 . The device of claim 1 , wherein
the first memory cell array includes
a first layered member in which first insulating films and first conductive films are layered alternately in a first direction, and
a plurality of first columnar members, each of which includes a first semiconductor portion and a charge trap film, the first semiconductor portion extending in the first layered member in the first direction and being electrically connected to the first wire layer, and the charge trap film being provided on an outer circumferential surface of the first semiconductor portion, and
the second memory cell array includes
a second layered member in which second insulating films and second conductive films are layered alternately in the first direction, and
a plurality of second columnar members, each of which includes a second semiconductor portion and a charge trap film, the second semiconductor portion extending in the second layered member in the first direction and being electrically connected to the first wire layer, and the charge trap film being provided on an outer circumferential surface of the second semiconductor portion.
5 . The device of claim 4 , wherein the first wire layer is connected in common to the first semiconductor portions of the first columnar members, and is connected in common to the second semiconductor portions of the second columnar members.