Stacked nanosheet FETs with gate dielectric fill
A semiconductor cell comprises a top FET that contains a first set of silicon nanosheets and a bottom FET that contains a second set of silicon nanosheets. The top FET and bottom FET are in a stacked profile. The semiconductor cell comprises a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets. The semiconductor cell also comprises a dielectric fill within the top FET cutout region.
1 . A semiconductor cell comprising:
a top field effect transistor (FET) that contains a first set of silicon nanosheets and a top-FET gate material;
a bottom FET that contains a second set of silicon nanosheets, wherein the top FET and bottom FET are in a stacked profile;
a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets; and
a dielectric fill within the top FET cutout region, wherein the top-FET gate material extends beneath the dielectric fill and in direct contact with a bottom surface of the dielectric fill.
2 . The semiconductor cell of claim 1 , further comprising:
a gate cap formed on the top-FET gate material and the dielectric fill.
3 . The semiconductor cell of claim 1 ,
wherein the top-FET gate material is formed between the dielectric fill and the first set of silicon nanosheets and upon a top surface of the dielectric fill.
4 . The semiconductor cell of claim 1 , further comprising a gate sidewall that is in the top FET cutout region and between the dielectric fill and the first set of silicon nanosheets.
5 . The semiconductor cell of claim 1 , further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets.
6 . The semiconductor cell of claim 1 , further comprising:
a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets; and
wherein the top gate material is located between the dielectric fill and the middle dielectric isolation layer.
7 . The semiconductor cell of claim 1 , further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets, wherein the dielectric fill and the middle dielectric isolation layer are composed of a same material.
8 . A set of semiconductor cells, the set of semiconductor cells comprising:
a first semiconductor cell with a first top FET cutout region, wherein a first dielectric fill is formed within the first top FET cutout region, wherein the first semiconductor includes a first plurality of nanosheets; and
a second semiconductor cell with a second top FET cutout region, wherein a second dielectric fill is formed within the second top FET cutout region, wherein the second semiconductor includes a second plurality of nanosheets, wherein the first dielectric fill is located a first distance from the second dielectric fill, wherein the first plurality of nanosheets is located a second distance from the second plurality of nanosheets, wherein the first distance is smaller than the second distance.
9 . The set of semiconductor cells of claim 8 , wherein the first dielectric fill and the second dielectric fill are a same dielectric fill.
10 . The set of semiconductor cells of claim 9 , further comprising a gate cap formed upon a top surface of the dielectric fill, wherein the gate cap spans a width of the first semiconductor cell and the second semiconductor cell.
11 . The set of semiconductor cells of claim 8 , further comprising a gate cut through between the first dielectric fill and the second dielectric fill.
12 . The set of semiconductor cells of claim 8 , further comprising:
a third semiconductor cell located horizontally with respect to the first semiconductor cell from a cross-gate-cut view perspective, wherein the third semiconductor cell comprises a third top FET cutout region, and wherein a third dielectric fill is formed within the third top FET cutout region.
13 . A semiconductor cell in a set of semiconductor cells, the semiconductor cell comprising:
a top field effect transistor (FET) that contains a first set of silicon nanosheets and a top-FET gate material;
a bottom FET that contains a second set of silicon nanosheets, wherein the top FET and the bottom FET are in a stacked profile;
a top FET cutout region lateral to the first set of nanosheets and above a portion of the second set of nanosheets; and
a dielectric fill within the top FET cutout region, wherein the top-FET gate material extends beneath the dielectric fill and in direct contact with a bottom surface of the dielectric fill.
14 . The semiconductor cell of claim 13 , further comprising:
a gate cap formed on the top-FET gate material and the dielectric fill.
15 . The semiconductor cell of claim 13 ,
wherein the top-FET gate material is formed between the dielectric fill and the first set of silicon nanosheets and upon a top surface of the dielectric fill.
16 . The semiconductor cell of claim 13 , further comprising a gate sidewall that is in the top FET cutout region and between the dielectric fill and the first set of silicon nanosheets.
17 . The semiconductor cell of claim 13 , further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets.
18 . The semiconductor cell of claim 13 , further comprising:
a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets; and
wherein the top gate material is located between the dielectric fill and the middle dielectric isolation layer.
19 . The semiconductor cell of claim 13 , further comprising a middle dielectric isolation layer between the first set of silicon nanosheets and the second set of silicon nanosheets, wherein the dielectric fill and the middle dielectric isolation layer are composed of a same material.