3D semiconductor device and structure with metal layers and memory cells
A 3D semiconductor device including: a first level including a first single crystal layer and first transistors, and at least one first metal layer-which includes interconnects between the first transistors forming control circuits-which overlays the first single crystal layer; a second metal layer overlaying first metal layer; a second level including second transistors, first memory cells (each including at least one second transistor) and overlaying second metal layer; a third level including third transistors (at least one includes a polysilicon channel), second memory cells (each including at least one third transistor and cell is partially disposed atop control circuits) and overlaying the second level; control circuits control data written to second memory cells; third metal layer disposed above third level; fourth metal layer includes a global power distribution grid, has a thickness at least twice the second metal layer, and is disposed above third metal layer.
1. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer overlays said first single crystal layer, and
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising forming first control circuits;
a second metal layer overlaying said at least one first metal layer;
a second level overlaying said second metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said control circuits,
wherein said first control circuits are connected to control data written to at least one of said second memory cells;
a third metal layer disposed above said third level; and
a fourth metal layer disposed above said third metal layer;
wherein at least one of said third transistors comprises a polysilicon channel,
wherein said fourth metal layer has a typical thickness which is at least twice a typical thickness of said second metal layer, and
wherein said fourth metal layer comprises a global power distribution grid.
2. The 3D semiconductor device according to claim 1 , further comprising:
a conductive path from said fourth metal layer to said second metal layer,
wherein said conductive path comprises a via disposed through said third level, and
wherein said via has a diameter of less than 1 micron.
3. The 3D semiconductor device according to claim 1 ,
wherein said second transistors are aligned to said first transistors with a less than 450 nm misalignment.
4. The 3D semiconductor device according to claim 1 ,
wherein at least one of said second transistors comprise a metal gate.
5. The 3D semiconductor device according to claim 1 , further comprising:
a top level disposed atop said fourth metal layer, and
wherein said top level comprises a second single crystal layer.
6. The 3D semiconductor device according to claim 1 ,
wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following a same lithography step.
7. The 3D semiconductor device according to claim 1 ,
wherein at least one of said second transistors comprises a portion being processed by a first lithography step, and
wherein at least one of said third transistors comprises a portion being processed by a second lithography step.
8. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer overlays said first single crystal layer, and
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising forming first control circuits;
a second metal layer overlaying said at least one first metal layer;
a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said control circuits,
wherein said first control circuits are connected to control data written to at least one of said second memory cells; and
a third metal layer disposed above said third level;
a fourth metal layer disposed above said third metal layer,
wherein at least one of said third transistors comprises a polysilicon channel,
wherein at least one of said second transistors comprises a metal gate,
wherein said fourth metal layer has a typical thickness which is at least twice a typical thickness of said second metal layer, and
wherein said device comprises at least one layer deposited using Atomic Layer Deposition (“ALD”).
9. The 3D semiconductor device according to claim 8 , further comprising:
a conductive path from said fourth metal layer to said second metal layer,
wherein said conductive path comprises a via disposed through said third level, and
wherein said via has a diameter of less than 1 micron.
10. The 3D semiconductor device according to claim 8 ,
wherein said fourth metal layer comprise global power distribution grid.
11. The 3D semiconductor device according to claim 8 ,
wherein said metal gate comprise tungsten.
12. The 3D semiconductor device according to claim 8 , further comprising:
a top level disposed atop said fourth metal layer,
wherein said top level comprises a second single crystal layer.
13. The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors is self-aligned to at least one of said third transistors, being processed following a same lithography step.
14. The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors comprises a portion being processed by a first lithography step, and
wherein at least one of said third transistors comprises a portion being processed by a second lithography step.
15. A 3D semiconductor device, the device comprising:
a first level comprising a first single crystal layer, said first level comprising a plurality of first transistors and at least one first metal layer,
wherein said at least one first metal layer overlays said first single crystal layer, and
wherein said at least one first metal layer comprises interconnects between said first transistors thus comprising forming first control circuits;
a second metal layer overlaying said at least one first metal layer;
a second level overlaying said at least one metal layer, said second level comprising a plurality of second transistors;
a third level overlaying said second level, said third level comprising a plurality of third transistors,
wherein said second level comprises a plurality of first memory cells, said first memory cells each comprising at least one of said second transistors,
wherein said third level comprises a plurality of second memory cells, said second memory cells each comprising at least one of said third transistors,
wherein at least one of said second memory cells is at least partially disposed atop of said control circuits,
wherein said first control circuits are connected to control data written to at least one of said second memory cells; and
a third metal layer disposed above said third level;
a fourth metal layer disposed above said third metal layer;
wherein at least one of said third transistors comprises a polysilicon channel,
wherein at least one of said second transistors comprises a portion being processed by a first lithography step,
wherein at least one of said third transistors comprises a portion being processed by a second lithography step,
wherein said fourth metal layer has a typical thickness which is at least twice a typical thickness of said second metal layer; and
a conductive path from said fourth metal layer to said second metal layer,
wherein said conductive path comprises a via disposed through said third level, and
wherein said via has a diameter of less than 1 micron.
16. The 3D semiconductor device according to claim 15 ,
wherein said fourth metal layer comprises a global power distribution grid.
17. The 3D semiconductor device according to claim 15 ,
wherein said device comprises at least one layer deposited using Atomic Layer Deposition (“ALD”).
18. The 3D semiconductor device according to claim 15 ,
wherein at least one of said second transistors comprises a metal gate.
19. The 3D semiconductor device according to claim 15 , further comprising:
a top level disposed atop said fourth metal layer, and
wherein said top level comprises a second single crystal layer.
20. The 3D semiconductor device according to claim 15 ,
wherein said first metal layer comprises tungsten.