Granted Patent B2

US 12,027,133 · App. 18/234,752 · Granted Jul 2, 2024

Inventor: Atsushi Umezaki (Kanagawa, JP)

Assignee: Semiconductor Energy Laboratory Co., Ltd.

G09G3/3674G02F1/13454G02F1/136286G09G3/3677G11C19/28H01L23/528H01L29/786G02F1/13606G02F2201/124G09G3/3688G09G2300/0408G09G2300/0417G09G2310/0286H01L27/1214H01L29/7869H01L2924/0002

Abstract

Claims (168)

1. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a scan line,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the scan line,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a first signal line,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,

wherein a gate of the fourth transistor is electrically connected to the first signal line,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a second signal line,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a power supply line,

wherein a gate electrode of the sixth transistor is electrically connected to a third signal line,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the power supply line,

wherein a gate electrode of the seventh transistor is electrically connected to a fourth signal line,

wherein in a plan view, an area where a first conductive layer serving as the one of the source electrode and the drain electrode of the first transistor overlaps with a second conductive layer serving as the gate electrode of the first transistor is larger than an area where a third conductive layer serving as the other of the source electrode and the drain electrode of the first transistor overlaps with the second conductive layer,

wherein in the plan view, the first conductive layer comprises a first region overlapping with the second conductive layer and sandwiched between regions of the third conductive layer,

wherein in the plan view, the third conductive layer comprises a second region overlapping with the second conductive layer and sandwiched between regions of the first conductive layer, and

wherein a width of the first conductive layer in the first region is larger than a width of the third conductive layer in the second region.

2. The semiconductor device according to claim 1 ,

wherein the third transistor comprises a multi-gate structure having channel regions connected in series, and

wherein the fifth transistor comprises a multi-gate structure having channel regions connected in series.

3. The semiconductor device according to claim 1 ,

wherein when the other of the source electrode and the drain electrode of the second transistor and the scan line are in an electrical conduction state through at least a channel region of the second transistor, a potential of the other of the source electrode and the drain electrode of the second transistor is supplied to the scan line through at least the channel region of the second transistor,

wherein when the other of the source electrode and the drain electrode of the third transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the third transistor, a potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the third transistor,

wherein when the other of the source electrode and the drain electrode of the fifth transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fifth transistor, the potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the fifth transistor, and

wherein when the first signal line and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fourth transistor, a potential of the first signal line is supplied to the gate electrode of the first transistor through the channel region of the fourth transistor.

4. The semiconductor device according to claim 1 ,

wherein a pixel comprises an eighth transistor,

wherein one of a source electrode and a drain electrode of the eighth transistor is electrically connected to a pixel electrode,

wherein the other of the source electrode and the drain electrode of the eighth transistor is electrically connected to a fifth signal line, and

wherein a gate electrode of the eighth transistor is electrically connected to the scan line.

5. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a scan line,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the scan line,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a first signal line,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,

wherein a gate of the fourth transistor is electrically connected to the first signal line,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a second signal line,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a power supply line,

wherein a gate electrode of the sixth transistor is electrically connected to a third signal line,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the power supply line,

wherein a gate electrode of the seventh transistor is electrically connected to a fourth signal line,

wherein in a plan view, an area where a first conductive layer serving as the one of the source electrode and the drain electrode of the first transistor overlaps with a second conductive layer serving as the gate electrode of the first transistor is larger than an area where a third conductive layer serving as the other of the source electrode and the drain electrode of the first transistor overlaps with the second conductive layer,

wherein in the plan view, the first conductive layer comprises a first region overlapping with the second conductive layer and sandwiched between regions of the third conductive layer,

wherein in the plan view, the third conductive layer comprises a second region overlapping with the second conductive layer and sandwiched between regions of the first conductive layer,

wherein a width of the first conductive layer in the first region is larger than a width of the third conductive layer in the second region, and

wherein a fourth conductive layer comprising a region serving as the gate electrode of the second transistor and a region serving as the gate electrode of the third transistor.

6. The semiconductor device according to claim 5 ,

wherein the third transistor comprises a multi-gate structure having channel regions connected in series, and

wherein the fifth transistor comprises a multi-gate structure having channel regions connected in series.

7. The semiconductor device according to claim 5 ,

wherein when the other of the source electrode and the drain electrode of the second transistor and the scan line are in an electrical conduction state through at least a channel region of the second transistor, a potential of the other of the source electrode and the drain electrode of the second transistor is supplied to the scan line through at least the channel region of the second transistor,

wherein when the other of the source electrode and the drain electrode of the third transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the third transistor, a potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the third transistor,

wherein when the other of the source electrode and the drain electrode of the fifth transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fifth transistor, the potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the fifth transistor, and

wherein when the first signal line and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fourth transistor, a potential of the first signal line is supplied to the gate electrode of the first transistor through the channel region of the fourth transistor.

8. The semiconductor device according to claim 5 ,

wherein a pixel comprises an eighth transistor,

wherein one of a source electrode and a drain electrode of the eighth transistor is electrically connected to a pixel electrode,

wherein the other of the source electrode and the drain electrode of the eighth transistor is electrically connected to a fifth signal line, and

wherein a gate electrode of the eighth transistor is electrically connected to the scan line.

9. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a scan line,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the scan line,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a first signal line,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,

wherein a gate of the fourth transistor is electrically connected to the first signal line,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a second signal line,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a power supply line,

wherein a gate electrode of the sixth transistor is electrically connected to a third signal line,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the power supply line,

wherein a gate electrode of the seventh transistor is electrically connected to a fourth signal line,

wherein in a plan view, an area where a first conductive layer serving as the one of the source electrode and the drain electrode of the first transistor overlaps with a second conductive layer serving as the gate electrode of the first transistor is larger than an area where a third conductive layer serving as the other of the source electrode and the drain electrode of the first transistor overlaps with the second conductive layer,

wherein in the plan view, the first conductive layer comprises a first region overlapping with the second conductive layer and sandwiched between regions of the third conductive layer,

wherein in the plan view, the third conductive layer comprises a second region overlapping with the second conductive layer and sandwiched between regions of the first conductive layer,

wherein a width of the first conductive layer in the first region is larger than a width of the third conductive layer in the second region, and

wherein a fourth conductive layer comprising a region serving as the other of the source electrode and the drain electrode of the third transistor and a region serving as the other of the source electrode and the drain electrode of the fifth transistor.

10. The semiconductor device according to claim 9 ,

wherein the third transistor comprises a multi-gate structure having channel regions connected in series, and

wherein the fifth transistor comprises a multi-gate structure having channel regions connected in series.

11. The semiconductor device according to claim 9 ,

wherein when the other of the source electrode and the drain electrode of the second transistor and the scan line are in an electrical conduction state through at least a channel region of the second transistor, a potential of the other of the source electrode and the drain electrode of the second transistor is supplied to the scan line through at least the channel region of the second transistor,

wherein when the other of the source electrode and the drain electrode of the third transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the third transistor, a potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the third transistor,

wherein when the other of the source electrode and the drain electrode of the fifth transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fifth transistor, the potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the fifth transistor, and

wherein when the first signal line and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fourth transistor, a potential of the first signal line is supplied to the gate electrode of the first transistor through the channel region of the fourth transistor.

12. The semiconductor device according to claim 9 ,

wherein a pixel comprises an eighth transistor,

wherein one of a source electrode and a drain electrode of the eighth transistor is electrically connected to a pixel electrode,

wherein the other of the source electrode and the drain electrode of the eighth transistor is electrically connected to a fifth signal line, and

wherein a gate electrode of the eighth transistor is electrically connected to the scan line.

13. A semiconductor device comprising:

a first transistor;

a second transistor;

a third transistor;

a fourth transistor;

a fifth transistor;

a sixth transistor; and

a seventh transistor,

wherein one of a source electrode and a drain electrode of the first transistor is electrically connected to a scan line,

wherein the other of the source electrode and the drain electrode of the first transistor is electrically connected to a clock signal line,

wherein one of a source electrode and a drain electrode of the second transistor is electrically connected to the scan line,

wherein one of a source electrode and a drain electrode of the third transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the third transistor is electrically connected to a gate electrode of the second transistor,

wherein one of a source electrode and a drain electrode of the fourth transistor is electrically connected to a first signal line,

wherein the other of the source electrode and the drain electrode of the fourth transistor is electrically connected to the gate electrode of the first transistor,

wherein a gate of the fourth transistor is electrically connected to the first signal line,

wherein one of a source electrode and a drain electrode of the fifth transistor is electrically connected to a gate electrode of the first transistor,

wherein a gate electrode of the fifth transistor is electrically connected to a second signal line,

wherein one of a source electrode and a drain electrode of the sixth transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the sixth transistor is electrically connected to a power supply line,

wherein a gate electrode of the sixth transistor is electrically connected to a third signal line,

wherein one of a source electrode and a drain electrode of the seventh transistor is electrically connected to the scan line,

wherein the other of the source electrode and the drain electrode of the seventh transistor is electrically connected to the power supply line,

wherein a gate electrode of the seventh transistor is electrically connected to a fourth signal line,

wherein in a plan view, an area where a first conductive layer serving as the one of the source electrode and the drain electrode of the first transistor overlaps with a second conductive layer serving as the gate electrode of the first transistor is larger than an area where a third conductive layer serving as the other of the source electrode and the drain electrode of the first transistor overlaps with the second conductive layer,

wherein in the plan view, the first conductive layer comprises a first region overlapping with the second conductive layer and sandwiched between regions of the third conductive layer,

wherein in the plan view, the third conductive layer comprises a second region overlapping with the second conductive layer and sandwiched between regions of the first conductive layer,

wherein a width of the first conductive layer in the first region is larger than a width of the third conductive layer in the second region,

wherein a fourth conductive layer comprising a region serving as the gate electrode of the second transistor and a region serving as the gate electrode of the third transistor, and

wherein a fifth conductive layer comprising a region serving as the other of the source electrode and the drain electrode of the third transistor and a region serving as the other of the source electrode and the drain electrode of the fifth transistor.

14. The semiconductor device according to claim 13 ,

wherein the third transistor comprises a multi-gate structure having channel regions connected in series, and

wherein the fifth transistor comprises a multi-gate structure having channel regions connected in series.

15. The semiconductor device according to claim 13 ,

wherein when the other of the source electrode and the drain electrode of the second transistor and the scan line are in an electrical conduction state through at least a channel region of the second transistor, a potential of the other of the source electrode and the drain electrode of the second transistor is supplied to the scan line through at least the channel region of the second transistor,

wherein when the other of the source electrode and the drain electrode of the third transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the third transistor, a potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the third transistor,

wherein when the other of the source electrode and the drain electrode of the fifth transistor and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fifth transistor, the potential at which the first transistor is turned off is supplied to the gate electrode of the first transistor through at least the channel region of the fifth transistor, and

wherein when the first signal line and the gate electrode of the first transistor are in an electrical conduction state through at least a channel region of the fourth transistor, a potential of the first signal line is supplied to the gate electrode of the first transistor through the channel region of the fourth transistor.

16. The semiconductor device according to claim 13 ,

wherein a pixel comprises an eighth transistor,

wherein one of a source electrode and a drain electrode of the eighth transistor is electrically connected to a pixel electrode,

wherein the other of the source electrode and the drain electrode of the eighth transistor is electrically connected to a fifth signal line, and

wherein a gate electrode of the eighth transistor is electrically connected to the scan line.

Priority Claims (1)

Continuity (9)