3D semiconductor device and structure with metal layers
A semiconductor device, the device including: a first silicon layer including a first single crystal silicon layer; a plurality of first transistors each including a single crystal channel; a first metal layer disposed over the plurality of first transistors; a second metal layer disposed over the first metal layer; a third metal layer disposed over the second metal layer; a second level including a plurality of second transistors, the second level disposed over the third metal layer; a fourth metal layer disposed over the second level; a fifth metal layer disposed over the fourth metal layer; a via disposed through the second level, where at least one of the plurality of second transistors includes a metal gate, where an average thickness of the fifth metal layer is greater than an average thickness of the third metal layer by at least 50%; and at least one Electrostatic discharge (“ESD”) structure.
1. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a plurality of first transistors each comprising a single-crystal channel;
a first metal layer disposed over said plurality of first transistors;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of second transistors, said second level is disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer;
a via disposed through said second level,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein processing of said second transistors comprises use of Atomic Layer Deposition (“ALD”), and
wherein an average thickness of said fifth metal layer is greater than an average thickness of said third metal layer by at least 50%; and
a third level comprising a second single crystal silicon layer,
wherein said third level is disposed over said fifth metal layer.
2. The device according to claim 1 ,
wherein an average thickness of said second level is less than two microns.
3. The device according to claim 1 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
4. The device according to claim 1 ,
wherein said via has a diameter of less than 450 nm.
5. The device according to claim 1 ,
wherein an average thickness of said second metal layer is greater than an average thickness of said third metal layer by at least 50%.
6. The device according to claim 1 ,
wherein an average thickness of said fifth metal layer is greater than an average thickness of said fourth metal layer by at least 50%.
7. The device according to claim 1 ,
wherein said fifth metal layer comprises a portion of a global power distribution grid.
8. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a plurality of first transistors each comprising a single crystal channel;
a first metal layer disposed over said plurality of first transistors;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer;
a via disposed through said second level,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein an average thickness of said fifth metal layer is greater than an average thickness of said third metal layer by at least 50%; and
at least one Electrostatic discharge (“ESD”) structure.
9. The device according to claim 8 ,
wherein an average thickness of said second level is less than two microns, and
wherein processing of said second transistors comprises use of Atomic Layer Deposition (“ALD”).
10. The device according to claim 8 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
11. The device according to claim 8 ,
wherein said via has a diameter of less than 450 nm.
12. The device according to claim 8 ,
wherein an average thickness of said second metal layer is greater than an average thickness of said third metal layer by at least 50%.
13. The device according to claim 8 ,
wherein an average thickness of said fifth metal layer is greater than an average thickness of said fourth metal layer by at least 50%.
14. The device according to claim 8 , further comprising:
a third level comprising a second single crystal silicon layer,
wherein said third level is disposed over said fifth metal layer.
15. A semiconductor device, the device comprising:
a first silicon layer comprising a first single crystal silicon layer;
a plurality of first transistors each comprising a single crystal channel;
a first metal layer disposed over said plurality of first transistors;
a second metal layer disposed over said first metal layer;
a third metal layer disposed over said second metal layer;
a second level comprising a plurality of second transistors, said second level disposed over said third metal layer;
a fourth metal layer disposed over said second level;
a fifth metal layer disposed over said fourth metal layer; and
a via disposed through said second level,
wherein at least one of said plurality of second transistors comprises a metal gate,
wherein an average thickness of said fifth metal layer is greater than an average thickness of said third metal layer by at least 50%, and
wherein an average thickness of said second metal layer is greater than an average thickness of said third metal layer by at least 50%.
16. The device according to claim 15 ,
wherein an average thickness of said second level is less than two microns, and
wherein processing of said second transistors comprises use of Atomic Layer Deposition (“ALD”).
17. The device according to claim 15 ,
wherein said fourth metal layer is aligned to said first metal layer with a less than 40 nm alignment error.
18. The device according to claim 15 ,
wherein said via has a diameter of less than 450 nm.
19. The device according to claim 15 ,
wherein an average thickness of said fifth metal layer is greater than an average thickness of said fourth metal layer by at least 50%.
20. The device according to claim 15 , further comprising:
a third level comprising a second single crystal silicon layer,
wherein said third level is disposed over said fifth metal layer.