Selective deposition of metal oxides using silanes as an inhibitor
The present disclosure relates to methods and apparatuses for selective deposition on a surface. In particular, a silicon-containing inhibitor can be used to selectively bind to a first region, thus inhibiting deposition of a material on that first region.
1 . A method for selective deposition comprising:
providing a surface of a semiconductor substrate including a first region and a second region, wherein the first region comprises a metal or a semiconductor and the second region comprises a different material than the first region;
introducing a silicon-containing inhibitor to the surface to provide an inhibitor layer on the first region, wherein the silicon-containing inhibitor comprises a formula RSiHX 1 X 2 , wherein R is an organic moiety and each of X 1 and X 2 is independently optionally substituted alkyl, optionally substituted alkenyl, optionally substituted alkynyl, optionally substituted cycloalkyl, or optionally substituted aryl; and
depositing a first layer on at least a portion of a non-inhibited surface comprising the second region.
2 . The method of claim 1 ,
wherein the first region comprises the metal, and
wherein the second region comprises a dielectric or a semiconductor.
3 . The method of claim 2 , wherein at least one of:
(i) the first region comprises copper (Cu), cobalt (Co), tungsten (W), ruthenium (Ru), tantalum (Ta), titanium (Ti), hafnium (Hf), zirconium (Zr), and/or molybdenum (Mo), and
(ii) the second region comprises silicon (Si), silicon dioxide (SiO 2 ), doped SiO 2 , silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, a low-K dielectric, germanium, silicon germanium, or germanium silicon.
4 . The method of claim 1 ,
wherein the first region comprises the semiconductor, and
wherein the second region comprises a dielectric.
5 . The method of claim 4 , wherein at least one of:
(i) the first region comprises silicon (Si), germanium (Ge), silicon germanium (SiGe), doped Si, or doped Ge, and
(ii) the second region comprises silicon dioxide (SiO 2 ), doped SiO 2 , silicon nitride, silicon carbide, silicon oxycarbide, silicon oxynitride, silicon carbon nitride, or a low-K dielectric.
6 . The method of claim 1 , wherein said introducing comprises a dose time of about 5 seconds to 600 seconds, a temperature of about 50° C. to 100° C., and/or a pressure of about 5 Torr to 10 Torr.
7 . The method of claim 1 , wherein the inhibitor layer comprises a self-assembled monolayer or a self-assembled multilayer.
8 . The method of claim 1 , wherein the organic moiety is or comprises optionally substituted aliphatic, optionally substituted heteroaliphatic, optionally substituted cycloaliphatic, optionally substituted cycloheteroaliphatic, optionally substituted aromatic, optionally substituted alkyl, optionally substituted alkenyl, optionally substituted alkynyl, optionally substituted heteroalkyl, optionally substituted heteroalkenyl, optionally substituted heteroalkynyl, optionally substituted cycloalkyl, optionally substituted cycloheteroalkyl, optionally substituted aryl, or optionally substituted heterocyclyl.
9 . The method of claim 8 , wherein at least one of:
(i) the organic moiety is or comprises a branched-chain hydrocarbon, (ii) the organic moiety comprises one or more halo substitutions, and
iii) the organic moiety comprises 6 to 20 carbon atoms within a linear chain, branched chain, or cyclic group.
10 . The method of claim 8 , wherein the organic moiety is or comprises —X-L-Z, and wherein:
X is a covalent bond, optionally substituted alkylene, optionally substituted alkenylene, optionally substituted alkynylene, optionally substituted alkyleneoxy, optionally substituted heteroalkylene, optionally substituted heteroalkenylene, optionally substituted heteroalkynylene, optionally substituted arylene, optionally substituted aryleneoxy, or optionally substituted heterocyclyldiyl;
L is a covalent bond, —CR 1 R 2 —, —CR 1 ═CR 2 —, —NR 1 —, —C(O)—, —C(O) NR 1 —, —NR 1 C(O)—, —C(O)O—, —OC(O)—, —S—, or —O—;
Z is hydrogen (H), optionally substituted alkyl, optionally substituted alkenyl, optionally substituted alkynyl, optionally substituted heteroalkyl, optionally substituted heteroalkenyl, optionally substituted heteroalkynyl, optionally substituted aryl, or optionally substituted heterocyclyl; and
each of R 1 and R 2 is, independently, H or optionally substituted alkyl.
11 . The method of claim 1 , wherein said depositing comprises atomic layer deposition (ALD) or chemical vapor deposition (CVD).
12 . The method of claim 1 ,
wherein the first layer comprises an oxide, a metal oxide, a nitride, a metal nitride, a carbide, a metal carbide, or an oxynitride, and
wherein the first layer optionally comprises aluminum oxide, zinc oxide, zirconium oxide, hafnium oxide, silicon oxide, silicon oxynitride, silicon nitride, or titanium oxide.
13 . The method of claim 1 , wherein said introducing is conducted at a first temperature that is lower than a second temperature during said depositing.
14 . The method of claim 1 , further comprising before said introducing:
pre-treating the surface with a plasma.
15 . The method of claim 1 , further comprising before said depositing:
annealing the inhibitor layer at a temperature of from about 250° C. to 350° C.
16 . The method of claim 1 , further comprising after said depositing:
further depositing a second layer on at least a portion of a surface of the first layer or the non-inhibited surface.
17 . The method of claim 1 , further comprising after the depositing or after the further depositing:
post-treating the surface to remove the inhibitor layer; and
optionally providing a patterned via comprising a metal, wherein the patterned via is configured to be electrically connected to the first region.
18 . An apparatus for selective deposition, the apparatus comprising:
a processing chamber;
a substrate holder in the processing chamber;
one or more gas inlets for flowing gases into the processing chamber;
a vacuum source for removing gases from the processing chamber;
a plasma generator for generating a plasma within the processing chamber; and
one or more controllers comprising machine-readable instructions for operating the one or more gas inlets, vacuum source, and plasma generator to deposit onto a semiconductor substrate, the machine-readable instructions of the one or more controllers comprising instructions for:
(a) optionally causing operation of the plasma generator to provide a plasma to pre-treat a surface of the semiconductor substrate;
(b) causing operation of the one or more gas inlets to flow a silicon-containing inhibitor into the processing chamber and provide an inhibitor layer on a first region of a semiconductor substrate held in the substrate holder,
wherein the first region comprises a metal or a semiconductor, wherein the semiconductor substrate further comprises a second region comprising a different material than the first region,
wherein the silicon-containing inhibitor comprises a formula RSiHX 1 X 2 , and
wherein R is an organic moiety and each of X 1 and X 2 is independently optionally substituted alkyl, optionally substituted alkenyl, optionally substituted alkynyl, optionally substituted cycloalkyl, or optionally substituted aryl;
(c) causing operation of the vacuum source to remove at least some of the silicon-containing inhibitor from the processing chamber;
(d) optionally causing operation of the substrate holder to anneal the inhibitor layer at a temperature of from about 250° C. to 350° C.; and
(e) causing operation of the one or more gas inlets to flow a first precursor to deposit a first layer on at least a portion of a non-inhibited surface comprising the second region.
19 . The apparatus of claim 18 , wherein the machine-readable instructions of the one or more controllers comprising instructions for:
(f) causing operation of the one or more gas inlets, after (e), to flow a second precursor to further deposit a second layer on at least a portion of a surface of the first layer or the non-inhibited surface; and
(g) optionally causing operation of the plasma generator, after (e) or (f), to provide a plasma to post-treat a surface of the semiconductor substrate to remove the inhibitor layer.
20 . An apparatus for selective deposition, the apparatus comprising:
a first processing chamber having a first substrate holder;
a second processing chamber having a second substrate holder;
a transfer module configured to transfer a semiconductor substrate from the first processing chamber to the second processing chamber;
one or more gas inlets for flowing gases into the first processing chamber and the second processing chamber;
a vacuum source for removing gases from the first processing chamber and/or the second processing chamber;
a plasma generator for generating a plasma within the first processing chamber and/or the second processing chamber; and
one or more controllers comprising machine-readable instructions for operating the one or more gas inlets, vacuum source, and plasma generator to deposit onto the semiconductor substrate, the machine-readable instructions of the one or more controllers comprising instructions for:
(a) optionally causing operation of the plasma generator to provide a plasma to the first processing chamber to pre-treat a surface of the semiconductor substrate;
(b) causing operation of the one or more gas inlets to flow a silicon-containing inhibitor into the first processing chamber and provide an inhibitor layer on a first region of a semiconductor substrate held in the substrate holder, wherein the first region comprises a metal or a semiconductor,
wherein the semiconductor substrate further comprises a second region comprising a different material than the first region,
wherein the silicon-containing inhibitor comprises a formula RSiHX 1 X 2 , and
wherein R is an organic moiety and each of X 1 and X 2 is independently optionally substituted alkyl, optionally substituted alkenyl, optionally substituted alkynyl, optionally substituted cycloalkyl, or optionally substituted aryl;
(c) causing operation of the vacuum source to remove at least some of the silicon-containing inhibitor from the first processing chamber;
(d) optionally causing operation of the first substrate holder to anneal the inhibitor layer at a temperature of from about 250° C. to 350° C.;
(e) causing operation of the transfer module to transfer the semiconductor substrate from the first processing chamber to the second processing chamber;
(f) optionally causing operation of the second substrate holder to anneal the inhibitor layer at a temperature of from about 250° C. to 350° C.;
(g) causing operation of the one or more gas inlets to flow a first precursor to the second processing chamber to deposit a first layer on at least a portion of a non-inhibited surface comprising the second region;
(h) optionally causing operation of the one or more gas inlets to flow a second precursor to the second processing chamber to further deposit a second layer on at least a portion of a surface of the first layer or the non-inhibited surface; and
(i) optionally causing operation of the plasma generator, after (g) or (h), to provide a plasma to the second processing chamber to post-treat a surface of the semiconductor substrate to remove the inhibitor layer.