3D memory cell structures with floating bodies
Various 3D memory cells, array architectures, and processes are disclosed. In an embodiment, a memory cell structure is provided that is formed by a process of alternately depositing multiple semiconductor layers and insulating layers to form a stack, forming vertical bit line holes through the stack using a deep trench process, and forming floating bodies in the semiconductor layers using an isotropic doping process through the bit line holes.
1 . A memory cell structure, formed by a process of:
alternately depositing multiple semiconductor layers and insulating layers to form a stack;
forming a vertical bit line opening through the stack using a deep trench etching process;
isotropically doping through the vertical bit line opening to form floating-body regions in the semiconductor layers, the floating-body regions having a conductivity type opposite to that of the semiconductor layers and defining internal side surfaces that surround the vertical bit-line opening;
depositing bit line material in the vertical bit line opening such that the bit line material contacts the internal side surfaces of the floating-body regions;
removing the insulating layers to expose surfaces of the semiconductor layers, the floating-body regions, and the bit line material, wherein the floating-body regions are isolated from one another;
forming a gate dielectric layer on the exposed surfaces of the semiconductor layers, the floating-body regions, and the bit line material; and
depositing gate material on the gate dielectric layer.
2 . The memory cell structure of claim 1 , wherein the isotropically doping process comprises one of plasma doping (PLAD), gas-phase doping, collisional plasma doping, or plasma immersion ion implantation (PIII).
3 . The memory cell structure of claim 1 , wherein the insulating layers comprise oxide or nitride layers.
4 . The memory cell structure of claim 1 , wherein the semiconductor layers comprise P-type or N-type doping.
5 . The memory cell structure of claim 1 , wherein the bit-line material comprises a conductor selected from metal or heavily-doped polysilicon, and the gate material comprises a conductor selected from metal or heavily-doped polysilicon.
6 . The memory cell structure of claim 1 , wherein the removal of the insulating layers is performed using an isotropic wet-etching process.
7 . The memory cell structure of claim 1 , wherein the gate-dielectric layer comprises a thin oxide layer or a high-K material layer selected from hafnium oxide (HfO 2 ), zirconium oxide (ZrO 2 ), or titanium oxide (TiO 2 ).
8 . The memory cell structure of claim 1 , wherein the gate-dielectric layer comprises a charge-trapping stack selected from oxide-nitride-oxide (ONO), oxide-nitride (ON), or oxide-nitride-oxide-nitride-oxide (ONONO).
9 . The memory cell structure of claim 1 , wherein the gate-dielectric layer comprises a material selected from:
(a) a ferroelectric layer comprising lead zirconate titanate (PZT), hafnium oxide (HfO 2 ) in orthorhombic crystal phase, or hafnium-zirconium oxide (HfZrO 2 );
(b) an adjustable resistive layer comprising hafnium oxide (HfO x ), titanium oxide (TiO x ), or tantalum oxide (TaO x );
(c) a phase-change layer comprising germanium-antimony-tellurium alloy (Ge 2 Sb 2 Te 5 ) or chalcogenide glass; or
(d) a ferromagnetic layer comprising iron-nickel (NiFe) or iron-cobalt (CoFe) alloys.