Granted Patent B2

US 12,652,781 · App. 18/344,422 · Granted Jun 9, 2026

Inventors: Kevin M. Gertiser (Carmel, IN); Chris Fruth (Kokomo, IN)

Assignee: BorgWarner US Technologies LLC

H02M1/327H02M1/0054H02P27/08H05K7/20154H05K7/20254H05K7/2049H05K7/20854H05K7/209H05K7/20927H10W40/037H10W40/22H10W40/255H10W40/43H10W40/611H10W40/641H10W40/778H10W70/481H10W70/611H10W70/65H10W90/00B60L3/003B60L15/007B60L15/08B60L15/20B60L50/40B60L50/51B60L50/60B60L50/64B60L53/20B60L53/22B60L53/62B60L2210/30B60L2210/40B60L2210/42B60L2210/44B60L2240/36B60R16/02G01R15/20G06F1/08G06F13/4004G06F2213/40H02J7/855H02J2207/20H02M1/0009H02M1/08H02M1/084H02M1/088H02M1/123H02M1/32H02M1/322H02M1/4258H02M1/44H02M3/33523H02M7/003H02M7/537H02M7/5387H02M7/53871H02M7/53875H02M7/5395H02P27/06H02P27/085H02P29/024H02P29/027H02P29/68H02P2207/05H03K19/20H05K1/145H05K1/181H05K1/182H05K5/0247H05K7/2039H05K2201/042H05K2201/10166H10D64/018H10W40/226H10W40/235H10W40/47H10W40/60H10W70/685H10W70/692H10W72/07331H10W72/07354H10W72/30H10W72/347H10W90/734H10W90/736

Abstract

Claims (32)

1 . A power module comprising:

a signal layer including a gate trace;

a first substrate having a first outer layer and a first inner layer;

a semiconductor die coupled to a surface of the first inner layer, the semiconductor die including a gate connected to the gate trace;

a second substrate having a second outer layer and a second inner layer, the semiconductor die coupled to a surface of the second inner layer; and

a sinter element disposed between the semiconductor die and the second inner layer,

wherein the second inner layer includes a body, the body including a step trench formed in a portion of the body corresponding to an edge of the semiconductor die.

2 . The power module of claim 1 , wherein a thickness of the sinter element is in a range from approximately 25 μm to approximately 50 μm.

3 . The power module of claim 1 , wherein a thickness of the sinter element is approximately 25 μm.

4 . The power module of claim 1 , wherein a depth of the step trench from a surface of the sinter element attached to the second inner layer to a bottom of the step trench is in a range from approximately 50 μm to approximately 75 μm.

5 . The power module of claim 1 , wherein a depth from a surface of the semiconductor die attached to the sinter element to a bottom surface of the step trench as defined by the body of the second inner layer is in a range from approximately 75 μm to approximately 100 μm.

6 . The power module of claim 1 , wherein the step trench is in the portion of the body corresponding to the edge of the semiconductor die so that a line extending from the edge of the semiconductor die to the body, in a direction orthogonal to the surface of the second inner layer, intersects the step trench.

7 . The power module of claim 1 , wherein a width of the step trench is in a range from approximately 400 μm to approximately 500 μm.

8 . The power module of claim 1 , wherein the signal layer is disposed on the body.

9 . The power module of claim 8 , wherein the signal layer includes a flex layer including an insulating material and an electrically conductive material, and wherein the electrically conductive material of the flex layer is the gate trace and is coupled to a gate of the semiconductor die.

10 . The power module of claim 1 , wherein the semiconductor die includes a source connection, wherein the source connection is coupled to the body of the second inner layer of the second substrate.

11 . The power module of claim 1 , wherein the second substrate further includes a middle layer between the second inner layer and the second outer layer,

wherein the middle layer includes a ceramic,

wherein the second outer layer includes a metal, and

wherein the second inner layer includes a direct bond copper metallization layer.

12 . The power module of claim 11 , wherein the step trench is in the direct bond copper metallization layer.

13 . An inverter comprising the power module of claim 1 .

14 . A vehicle comprising the inverter of claim 13 .

15 . A power module, comprising:

a signal layer including a gate trace;

a first substrate;

a second substrate including a trench extending from a surface of the second substrate into a conducting body of the second substrate at a depth less than a thickness of the conducting body;

a semiconductor die disposed between the first substrate and the second substrate, the semiconductor die having a drain connection coupled to the first substrate, a source connection coupled to the second substrate, and a gate coupled to the gate trace; and

a sinter element disposed between the semiconductor die and the second substrate, the sinter element having a thickness in a range of 25 μm to 50 μm;

wherein the surface of the second substrate is attached to the sinter element.

16 . The power module of claim 15 , wherein the trench is etched into the conducting body of the second substrate in a portion of the second substrate corresponding to an edge of the semiconductor die.

17 . The power module of claim 15 , wherein a width of the trench is in a range of 400 μm to 500 μm.

Assignments (2)

Continuity (5)

References Cited (263)