Granted Patent B2

US 12,348,221 · App. 18/344,631 · Granted Jul 1, 2025

Inventors: Alexander Dribinsky (Naperville, IL); Tae Youn Kim (Irvine, CA); Dylan J. Kelly (San Diego, CA); Christopher N. Brindle (Poway, CA)

Assignee: pSemi Corporation

H03K17/161H03K17/102H03K17/284H03K17/6874H03K17/689H03K17/04H03K17/06H03K17/08H03K2217/0009

Abstract

Claims (25)

1. A switch circuit comprising:

a plurality of series-coupled transistors configured to selectively couple a signal from an input of the plurality of series-coupled transistors to an output of the plurality of series-coupled transistors based on a switch control signal applied to each transistor of the plurality of series-coupled transistors, wherein a transistor of the plurality of series-coupled transistors is configured to operate in an off state or an on state based on the switch control signal applied to the transistor, wherein the transistor comprises a gate and an accumulated charge sink (ACS) coupled to the gate, and wherein the ACS is configured to control accumulated charge in the transistor when the transistor is operated in the off state; and

a plurality of charge injection control resistors, wherein each charge injection control resistor of the plurality of charge injection control resistors has at least one end coupled to a node between two transistors of the plurality of series-coupled transistors to control injected charge at the node.

2. The switch circuit of claim 1 , wherein, for each of the plurality of charge injection control resistors, the at least one end is coupled to the node to control the injected charge at the node by receiving the injected charge from the node and conveying the injected charge to the input and/or the output of the plurality of series-coupled transistors.

3. The switch circuit of claim 1 , wherein each transistor of the plurality of series-coupled transistors comprises a metal-oxide-semiconductor field effect transistor (MOSFET).

4. The switch circuit of claim 1 , further comprising a resistor having a resistance Rg and coupled to one of the plurality of series-coupled transistors, wherein the plurality of series-coupled transistors comprises a plurality of N transistors, and wherein an impedance of at least one charge injection control resistor of the plurality of charge injection control resistors is in the range between 10 Rg/N and Rg/10N.

5. The switch circuit of claim 1 , wherein at least one charge injection control resistor of the plurality of charge injection control resistors has an impedance sufficiently low to control the injected charge at the node to which the at least one end of the at least one charge injection control resistor is coupled and/or avoid degradation of a switching time associated with the switch circuit.

6. The switch circuit of claim 5 , wherein the impedance of the at least one charge injection control resistor is sufficiently high to prevent degradation of isolation performance associated with the switch circuit.

7. The switch circuit of claim 5 , further comprising a resistor having a resistance Rg and coupled to one of the plurality of series-coupled transistors.

8. The switch circuit of claim 7 , wherein the plurality of series-coupled transistors comprises a plurality of N transistors, and wherein the impedance of the at least one charge injection control resistor is in the range between 10 Rg/N and Rg/10N.

9. The switch circuit of claim 7 , wherein the resistance Rg of the resistor is at least ten times larger than an impedance of a gate-to-drain capacitance associated with the one of the plurality of series-coupled transistors.

10. The switch circuit of claim 7 , wherein the impedance of the at least one charge injection control resistor is smaller than the resistance Rg of the resistor.

11. The switch circuit of claim 7 , wherein the plurality of series-coupled transistors comprises a plurality of N transistors, and wherein the impedance of the at least one charge injection control resistor is greater than or equal to about Rg/N.

12. The switch circuit of claim 7 , wherein the plurality of series-coupled transistors comprises a plurality of N transistors, and wherein the impedance of the at least one charge injection control resistor is approximately equal to Rg/N.

13. The switch circuit of claim 1 , further comprising a diode coupled to the gate and the ACS, wherein the diode is configured to selectively convey accumulated charge from the ACS to the gate.

14. A method comprising:

selectively coupling a signal from an input of a plurality of series-coupled transistors to an output of the plurality of series-coupled transistors based on a switch control signal applied to each transistor of the plurality of series-coupled transistors, wherein a transistor of the plurality of series-coupled transistors selectively operates in an off state or an on state based on the switch control signal applied to the transistor, wherein the transistor comprises a gate and an accumulated charge sink (ACS) coupled to the gate;

controlling, by a plurality of charge injection control resistors, injected charge at nodes of the plurality of series-coupled transistors, wherein each of the nodes is between two transistors of the plurality of series-coupled transistors; and

controlling, by the ACS, accumulated charge in the transistor when the transistor is operated in the off state.

15. The method of claim 14 , wherein the controlling the injected charge comprises receiving, by the plurality of charge injection control resistors, the injected charge from the nodes and conveying the injected charge to the input and/or the output of the plurality of series-coupled transistors.

16. The method of claim 14 , wherein each transistor of the plurality of series-coupled transistors comprises a metal-oxide-semiconductor field effect transistor (MOSFET).

17. The method of claim 14 , wherein at least one charge injection control resistor of the plurality of charge injection control resistors has an impedance sufficiently low to control the injected charge at one or more of the nodes and/or sufficiently high to prevent degradation of isolation performance associated with the plurality of series-coupled transistors and the plurality of charge injection control resistors.

18. The method of claim 14 , wherein the plurality of series-coupled transistors comprises a plurality of N transistors, wherein a resistor has a resistance Rg and is coupled to one of the plurality of series-coupled transistors, and wherein an impedance of at least one charge injection control resistor of the plurality of charge injection control resistors is in the range between 10 Rg/N and Rg/10N.

19. The method of claim 14 , wherein the controlling the accumulated charge in the transistor comprises applying a series of voltage pulses to the gate of the transistor.

20. The method of claim 14 , wherein the controlling the accumulated charge comprises conveying the accumulated charge from the ACS of the transistor to the gate of the transistor.

Assignments (2)

Continuity (13)

References Cited (281)