Method and memory used for reducing program disturbance by adjusting voltage of dummy word line
A method for operating a memory device is provided. The memory device includes a first word line, a second word line, a first dummy word line, and a second dummy word line. The first dummy word line and the second dummy word line are between the first word line and the second word line. A first pass voltage is applied to the first dummy word line in a program operation. A second pass voltage is applied to the second dummy word line in the program operation. The first pass voltage is different from the second pass voltage.
1 . A method for operating a memory device, the memory device comprising a first word line, a second word line, a first dummy word line, a second dummy word line, and a third dummy word line, wherein the first dummy word line, the second dummy word line, and the third dummy word line are between the first word line and the second word line, and the third dummy word line is between the first word line and the first dummy word line, the method comprising:
applying a first pass voltage to the first dummy word line in a program operation;
applying a second pass voltage to the second dummy word line in the program operation, wherein the first pass voltage is different from the second pass voltage; and
applying a third pass voltage to the third dummy word line in the program operation, wherein the first pass voltage is greater than the second pass voltage, and the third pass voltage is greater than the first pass voltage and the second pass voltage.
2 . The method of claim 1 , wherein
the memory device further comprises a Top Select Gate (TSG) line and a Bottom Select Gate (BSG) line, the first word line is between the TSG line and the first dummy word line, the second dummy word line and the second word line are between the first dummy word line and 1.
3 . The method of claim 2 , wherein a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell coupled to the first dummy word line is greater than a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell coupled to the second dummy word line.
4 . The method of claim 3 , wherein the first voltage difference minus the second voltage difference is more than 3 V and less than 7 V.
5 . The method of claim 3 , wherein the first threshold voltage of the first dummy cell is the same as the second threshold voltage of the second dummy cell.
6 . The method of claim 3 , wherein the first threshold voltage of the first dummy cell is different from the second threshold voltage of the second dummy cell.
7 . The method of claim 3 , further comprising:
applying a pre-pulse voltage to the first dummy word line and the second dummy word line in a pre-pulse operation before the program operation.
8 . The method of claim 7 , wherein the pre-pulse voltage is higher than the first threshold voltage of the first dummy cell and the second threshold voltage of the second dummy cell.
9 . The method of claim 2 , further comprising:
applying a programming voltage to the first word line in the program operation when a memory cell coupled to the first word line being programed.
10 . The method of claim 1 , wherein
the memory device further comprises a fourth dummy word line between the second dummy word line and the second word line; and
the method further comprises applying a fourth pass voltage to the fourth dummy word line in the program operation, the third pass voltage being greater than the fourth pass voltage and the second pass voltage.
11 . A method for operating a memory device, the memory device comprising a first deck and a second deck, the first deck being formed over the second deck, the first deck comprising a first word line, a first dummy word line, and a third dummy word line, the second deck comprising a second word line and a second dummy word line, wherein the first dummy word line, the second dummy word line, and the third dummy word line are between the first word line and the second word line, and the third dummy word line is between the first word line and the first dummy word line, the method comprising:
applying a first pass voltage to the first dummy word line in a program operation;
applying a second pass voltage to the second dummy word line in the program operation; and
applying a third pass voltage to the third dummy word line in the program operation, wherein the first pass voltage is greater than the second pass voltage, and the third pass voltage is greater than the first pass voltage and the second pass voltage.
12 . The method of claim 11 , wherein,
wherein a first voltage difference between the first pass voltage and a first threshold voltage of a first dummy cell coupled to the first dummy word line is different from a second voltage difference between the second pass voltage and a second threshold voltage of a second dummy cell coupled to the second dummy word line, and
the first voltage difference is greater than the second voltage difference.
13 . The method of claim 12 , wherein the first voltage difference minus the second voltage difference is more than 3 V and less than 7 V.
14 . A memory device, comprising:
a memory cell array comprising:
a first word line;
a second word line;
a first dummy word line;
a second dummy word line; and
a third dummy word line, wherein the first dummy word line, the second dummy word line, and the third dummy word line are between the first word line and the second word line, and the third dummy word line is between the first word line and the first dummy word line; and
a control circuit coupled to the memory cell array and configured to:
apply a first pass voltage to the first dummy word line in a program operation;
apply a second pass voltage to the second dummy word line in the program operation, wherein the first pass voltage is different from the second pass voltage; and
apply a third pass voltage to the third dummy word line in the program operation, wherein the first pass voltage is greater than the second pass voltage, and the third pass voltage is greater than the first pass voltage and the second pass voltage.
15 . The memory device of claim 14 , wherein
the memory cell array further comprises a Top Select Gate (TSG) line and a Bottom Select Gate (BSG) line, the first word line is between the TSG line and the first dummy word line, and the second dummy word line and the second word line are between the first dummy word line and the BSG line.
16 . The memory device of claim 14 , wherein the control circuit is configured to:
apply a programming voltage to the first word line in the program operation when a memory cell coupled to the first word line being programed.
17 . The memory device of claim 14 , wherein the control circuit is configured to:
apply a pre-pulse voltage to the first dummy word line and the second dummy word line in a pre-pulse operation before the program operation.
18 . The memory device of claim 14 , further comprising a joint oxide layer between a first deck and a second deck.
19 . The memory device of claim 18 , wherein the first dummy word line is between the joint oxide layer and the first word line, and the second dummy word line is between the joint oxide layer and the second word line.