IP Library › Granted Patent US 12,278,280
Granted Patent B2
US 12,278,280 · App. 18/432,923 · Granted Apr 15, 2025

Method of manufacturing semiconductor device

Inventor: Katsumi Nakamura (Tokyo, JP)
Assignee: Mitsubishi Electric Corporation
H01L29/7397H01L29/0696H01L29/66333H01L29/868
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Quick Facts
Patent No.
US 12,278,280
App. No.
18/432,923
Granted
Apr 15, 2025
Kind
B2
Abstract

A semiconductor device includes: an N − drift layer of a first conductivity type formed in the semiconductor substrate; a P base layer formed on the N − drift layer; and an N buffer layer of the first conductivity type formed under the N − drift layer and higher in peak impurity concentration than the N − drift layer. The N buffer layer includes: a first buffer layer in which a trap level derived from lattice defect is not detected by a photoluminescence method; and a second buffer layer provided between the first buffer layer and the N − drift layer and in which two types of trap levels derived from lattice defect are detected by the photoluminescence method.

Claims (19)

1. A method of manufacturing a semiconductor device comprising the steps of:

(a) forming a predetermined device structure in a semiconductor substrate with a first main surface and a second main surface and in which a drift layer is formed;

(b) recovering carrier lifetime in the drift layer after the step (a) in such a manner that the carrier lifetime becomes equal to or greater than τ t expressed as 1.5×10 −5 exp(5.4×10 3 t N- ) while t N- means the thickness of the drift layer;

(c) forming an electrode and a protective film for protecting the electrode on the first main surface of the semiconductor substrate after the step (b); and

(d) forming a buffer layer on the drift layer to be closer to the second main surface after the step (c), the buffer layer including a first buffer layer and a second buffer layer provided between the first buffer layer and the drift layer,

the step (b) comprising the steps of:

(b-1) exposing the second main surface of the semiconductor substrate by etching;

(b-2) forming polysilicon doped with impurity of a first conductivity type on the second main surface of the semiconductor substrate; and

(b-3) forming a high-concentration layer of the first conductivity type and a high crystal defect density layer on the second main surface of the semiconductor substrate after the step (b-2) by performing first annealing in a nitrogen atmosphere at a first temperature and performing second annealing in a nitrogen atmosphere at a second temperature while the first temperature is reduced to the second temperature lower than the first temperature,

the step (d) comprising the steps of:

(d-1) removing the high-concentration layer and the high crystal defect density layer from the second main surface of the semiconductor substrate and controlling the thickness of the semiconductor substrate by polishing or etching;

(d-2) introducing impurity for the first buffer layer into the semiconductor substrate from the second main surface after the step (d-1);

(d-3) annealing the semiconductor substrate to form the first buffer layer after the step (d-2);

(d-4) introducing impurity for the second buffer layer into the semiconductor substrate from the second main surface after the step (d-3); and

(d-5) annealing the semiconductor substrate to form the second buffer layer after the step (d-4).

2. The method of manufacturing the semiconductor device according to claim 1 , wherein

a temperature of the annealing in the step (d-5) is from 370 to 425° C.

3. The method of manufacturing the semiconductor device according to claim 1 , wherein

time of the annealing in the step (d-5) is equal to or greater than 90 minutes.

Assignments (1)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 6, 2024
From: NAKAMURA, KATSUMI
To: MITSUBISHI ELECTRIC CORPORATION
Reel/Frame 066396/0175 →
Priority Claims (1)
JP 2020-183522 · Nov 2, 2020 · national
Continuity (2)
Division 17405451 · Aug 18, 2021
Related Publication 20240178306A1 · May 30, 2024
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