Polysilicon resistor structures
View Patent ↗The present disclosure describes a method for forming polysilicon resistors with high-k dielectrics and polysilicon gate electrodes. The method includes depositing a resistor stack on a substrate having spaced apart first and second isolation regions. Further the method includes patterning the resistor stack to form a polysilicon resistor structure on the first isolation region and a gate structure between the first and second isolation regions, and doping the polysilicon resistor structure to form a doped layer in the polysilicon layer of the polysilicon resistor structure and source-drain regions in the substrate adjacent to the gate structure. Also, the method includes replacing the polysilicon layer in the gate structure with a metal gate electrode to form a transistor structure.
1. A method, comprising:
forming a resistor stack on a substrate, comprising:
forming a dielectric layer on the substrate;
forming a metal nitride layer on the dielectric layer; and
forming a polysilicon layer on the metal nitride layer;
patterning the resistor stack to form a resistor structure;
doping an upper portion of the polysilicon layer to form a doped polysilicon layer;
forming a silicide layer covering an entire top surface of the doped polysilicon layer; and
forming a contact structure on the silicide layer to direct current through the resistor structure along a length of the resistor structure.
2. The method of claim 1 , wherein doping the upper portion of the polysilicon layer comprises ion implanting the upper portion of the polysilicon layer with an n-type dopant or a p-type dopant.
3. The method of claim 2 , wherein doping the upper portion of the polysilicon layer further comprises:
forming a sacrificial hard mask layer on the polysilicon layer; and
controlling a depth of the doped polysilicon layer by modulating a thickness of the sacrificial hard mask layer.
4. The method of claim 1 , wherein forming the silicide layer comprises:
depositing a metal layer on the doped polysilicon layer; and
annealing the metal layer to form the silicide layer.
5. A method, comprising:
forming, on a substrate, a polysilicon resistor stack structure concurrently with a transistor, wherein forming the polysilicon resistor stack structure comprises:
forming a dielectric layer on the substrate;
forming a metal nitride layer on the dielectric layer; and
forming a polysilicon layer on the metal nitride layer;
simultaneously doping the polysilicon layer and a source/drain region of the transistor; and
siliciding an entire top surface of the doped polysilicon layer to form a silicide layer.
6. The method of claim 5 , wherein doping the polysilicon layer comprises forming a doped polysilicon layer and an un-doped polysilicon layer within the polysilicon layer.
7. The method of claim 5 , wherein doping the polysilicon layer comprises forming a fully-doped polysilicon layer.
8. The method of claim 5 , further comprising patterning the polysilicon resistor stack structure to form a polysilicon resistor structure.
9. The method of claim 8 , further comprising forming a dielectric layer surrounding the polysilicon resistor structure and the transistor.
10. The method of claim 5 , further comprising forming a contact structure on the silicide layer.
11. The method of claim 5 , wherein simultaneously doping the polysilicon layer and the source/drain region of the transistor comprises doping the polysilicon layer and the source/drain region of the transistor with a same dopant species.
12. A method comprising:
forming a stacked polysilicon resistor on a substrate, the stacked polysilicon resistor comprising:
a doped polysilicon layer disposed on an un-doped polysilicon layer; and
a silicide layer disposed on the doped polysilicon layer;
forming a sidewall spacer in contact with the stacked polysilicon resistor; and
forming a contact structure on the silicide layer.
13. The method of claim 12 , wherein forming the doped polysilicon layer comprises forming the doped polysilicon layer at a depth of about 5 nm and about 200 nm from a top surface of the polysilicon layer.
14. The method of claim 12 , further comprising forming an etch stop layer surrounding the sidewall spacer.
15. The method of claim 12 , further comprising forming a first dielectric layer surrounding the stacked polysilicon resistor.
16. The method of claim 15 , further comprising forming a second dielectric layer on the first dielectric layer.
17. The method of claim 1 , further comprising forming spacer structures on sidewall surfaces of the resistor stack.
18. The method of claim 17 , further comprising forming an etch stop layer surrounding the spacer structures.
19. The method of claim 5 , further comprising forming spacer structures on sidewall surfaces of the polysilicon resistor stack structure.
20. The method of claim 19 , further comprising forming an etch stop layer surrounding spacer structures.