Methods for forming three-dimensional memory devices
A method for forming a three-dimensional (3D) memory device is disclosed. An array of NAND memory strings is formed on a first substrate. A first semiconductor layer is formed above the array of NAND memory strings. The first semiconductor layer includes single crystalline silicon. A first transistor is formed on the first semiconductor layer. A second semiconductor layer is formed above the first transistor. The second semiconductor layer includes single crystalline silicon. A second transistor is formed on the second semiconductor layer.
1. A method for forming a three-dimensional (3D) memory device, comprising:
forming an array of NAND memory strings on a first substrate;
forming a first semiconductor layer above the array of NAND memory strings, wherein the first semiconductor layer comprises single crystalline silicon;
forming a first transistor on the first semiconductor layer;
forming a second semiconductor layer above the first transistor, wherein the second semiconductor layer comprises single crystalline silicon;
forming a second transistor on the second semiconductor layer;
thinning the first substrate after forming the second transistor; and
forming a pad-out interconnect layer above the array of NAND memory strings.
2. The method of claim 1 , further comprising:
forming a first contact through the first semiconductor layer before forming the second semiconductor layer; and
forming a second contact through the second semiconductor layer.
3. The method of claim 1 , wherein forming the first semiconductor layer comprises:
bonding a second substrate and the first substrate; and
thinning the second substrate to leave the first semiconductor layer.
4. The method of claim 3 , wherein forming the second semiconductor layer comprises:
bonding a third substrate and the first substrate; and
thinning the third substrate to leave the second semiconductor layer.
5. The method of claim 4 , wherein bonding the second and first substrates and bonding the third and first substrates each comprises transfers bonding.
6. The method of claim 1 , wherein
forming the first transistor comprises forming a first gate dielectric; and
forming the second transistor comprises forming a second gate dielectric,
wherein a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.
7. The method of claim 6 , wherein a difference between the thicknesses of the first and second gate dielectrics is at least 5-fold.
8. The method of claim 6 , further comprising:
forming a third transistor on the first semiconductor layer; and
forming a fourth transistor on the second semiconductor layer,
wherein forming the third transistor comprises forming a third gate dielectric, forming the fourth transistor comprises forming a fourth gate dielectric, and the third and fourth gate dielectrics have a same thickness.
9. The method of claim 8 , wherein the thickness of the third and fourth gate dielectrics is between the thicknesses of the first and second gate dielectrics.
10. The method of claim 1 , wherein a thickness of the first semiconductor layer is greater than a thickness of the second semiconductor layer.
11. The method of claim 1 , further comprising forming contact pads in the pad-out interconnect layer.
12. The method of claim 11 , wherein contact pads comprise copper.
13. A method for forming a three-dimensional (3D) memory device, comprising:
forming an array of NAND memory strings on a first substrate;
forming a first transistor on a second substrate;
forming a second transistor on a third substrate;
bonding the first substrate and second substrate in a face-to-back manner;
bonding the second substrate and the third substrate in a face-to-back manner;
thinning the first substrate after bonding the first and second substrates and bonding the second and third substrates; and
forming a pad-out interconnect layer above the array of NAND memory strings.
14. The method of claim 13 , further comprising:
thinning the second substrate before bonding the first and second substrates; and
forming a first contact through the thinned second substrate.
15. The method of claim 14 , further comprising:
thinning the third substrate before bonding the second and third substrates; and
forming a second contact through the thinned third substrate such that the second contact is coupled to the first contact after bonding the thinned second and third substrates.
16. The method of claim 13 , wherein
forming the first transistor comprises forming a first gate dielectric; and
forming the second transistor comprises forming a second gate dielectric,
wherein a thickness of the first gate dielectric is greater than a thickness of the second gate dielectric.
17. A method for forming a three-dimensional (3D) memory device, comprising:
forming a first semiconductor structure including an array of NAND memory strings on a first substrate;
forming a second semiconductor structure, comprising:
forming a first peripheral circuit of the array of NAND memory strings on a second substrate,
thinning the second substrate, and
forming a first contact through the thinned second substrate;
forming a third semiconductor structure including a second peripheral circuit of the array of NAND memory strings on a third substrate;
bonding the first semiconductor structure and second semiconductor structure, such that the second substrate is between the array of NAND memory strings and the first peripheral circuit; and
bonding the second substrate and the third substrate, such that the third substrate is between the first peripheral circuit and the second peripheral circuit.
18. The method of claim 17 , forming the third semiconductor structure further comprises:
thinning the third substrate; and
forming a second contact through the thinned third substrate.
19. The method of claim 18 , further comprising:
thinning the first substrate; and
forming a pad-out interconnect layer on the thinned first substrate and coupled with the second peripheral circuit through the first contact and the second contact.
20. The method of claim 17 , further comprising:
forming a pad-out interconnect layer on the second peripheral circuit and coupled with the array of NAND memory strings through the first contact and the second contact.