Sequential erase for tuning the program state of non-volatile memory cells
A method and device for erasing a memory cell with a floating gate, by applying successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current, and then applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved. The first erase pulses include a first parameter following a first progression that changes in value after respective ones of the first erase pulses. The first progression begins with a first value and ends with a second value. The second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses. The second progression begins with a third value that is between, and unequal to, the first and second values.
1 . A method of erasing a memory cell including a floating gate, comprising:
applying successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current for the memory cell is achieved, wherein the first erase pulses include a first parameter following a first progression in which the first parameter changes in value after respective ones of the first erase pulses and wherein the first progression begins with a first value of the first parameter and ends with a second value of the first parameter; and
after the coarse target read current is achieved, applying successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved, wherein the second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses,
wherein the second progression begins with a third value of the first parameter that is between, and unequal to, the first and second values.
2 . The method of claim 1 , wherein:
the first parameter is a voltage applied to the memory cell;
during the first progression, the voltage increases in value after respective ones of the first erase pulses, wherein the second value is greater than the first value;
during the second progression, the voltage increases in value after respective ones of the second erase pulses; and
the third value is less than the second value.
3 . The method of claim 1 , wherein:
the first parameter is a voltage applied to the memory cell;
during the first progression, the voltage decreases in value after respective ones of the first erase pulses, wherein the second value is less than the first value;
during the second progression, the voltage decreases in value after respective ones of the second erase pulses; and
the third value is greater than the second value.
4 . The method of claim 1 , wherein:
the first parameter is a duration of respective ones of the first and second erase pulses;
during the first progression, the duration increases in value after respective ones of the first erase pulses, wherein the second value is greater than the first value;
during the second progression, the duration increases in value after respective ones of the second erase pulses; and
the third value is less than the second value.
5 . The method of claim 1 , wherein:
during the first progression, the first parameter changes in value by a first change value after respective ones of the first erase pulses;
during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses; and
the second change value is equal to the first change value.
6 . The method of claim 1 , wherein:
during the first progression, the first parameter changes in value by a first change value after respective ones of the first erase pulses;
during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses; and
the second change value is less than the first change value.
7 . The method of claim 2 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region; and
a select gate disposed over and insulated from a second portion of the channel region,
wherein the voltage applied to the memory cell is applied to the select gate.
8 . The method of claim 2 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region;
a select gate disposed over and insulated from a second portion of the channel region; and
an erase gate disposed over and insulated from the source region,
wherein the voltage applied to the memory cell is applied to the erase gate.
9 . The method of claim 2 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region;
a select gate disposed over and insulated from a second portion of the channel region;
an erase gate disposed over and insulated from the source region; and
a control gate disposed over and insulated from the floating gate,
wherein the voltage applied to the memory cell is applied to the erase gate.
10 . The method of claim 3 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region;
a select gate disposed over and insulated from a second portion of the channel region;
an erase gate disposed over and insulated from the source region; and
a control gate disposed over and insulated from the floating gate,
wherein the voltage applied to the memory cell is applied to the control gate.
11 . A semiconductor device, comprising:
a memory cell including a floating gate; and
a control circuitry to:
apply successive first erase pulses to the memory cell to remove electrons from the floating gate until a coarse target read current for the memory cell is achieved, wherein the first erase pulses include a first parameter following a first progression in which the first parameter changes in value after respective ones of the first erase pulses and wherein the first progression begins with a first value of the first parameter and ends with a second value of the first parameter; and
after the coarse target read current is achieved, apply successive second erase pulses to the memory cell to remove electrons from the floating gate until a target read current for the memory cell is achieved, wherein the second erase pulses include the first parameter following a second progression in which the first parameter changes in value after respective ones of the second erase pulses,
wherein the second progression begins with a third value of the first parameter that is between, and unequal to, the first and second values.
12 . The semiconductor device of claim 11 , wherein:
the first parameter is a voltage applied to the memory cell;
during the first progression, the voltage increases in value after respective ones of the first erase pulses, wherein the second value is greater than the first value;
during the second progression, the voltage increases in value after respective ones of the second erase pulses; and
the third value is less than the second value.
13 . The semiconductor device of claim 11 , wherein:
the first parameter is a voltage applied to the memory cell;
during the first progression, the voltage decreases in value after respective ones of the first erase pulses, wherein the second value is less than the first value;
during the second progression, the voltage decreases in value after respective ones of the second erase pulses; and
the third value is greater than the second value.
14 . The semiconductor device of claim 11 , wherein:
the first parameter is a duration of respective ones of the first and second erase pulses;
during the first progression, the duration increases in value after respective ones of the first erase pulses, wherein the second value is greater than the first value;
during the second progression, the duration increases in value after respective ones of the second erase pulses; and
the third value is less than the second value.
15 . The semiconductor device of claim 11 , wherein:
during the first progression, the first parameter changes in value by a first change value after respective ones of the first erase pulses;
during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses; and
the second change value is equal to the first change value.
16 . The semiconductor device of claim 11 , wherein:
during the first progression, the first parameter changes in value by a first change value after respective ones of the first erase pulses;
during the second progression, the first parameter changes in value by a second change value after respective ones of the second erase pulses; and
the second change value is less than the first change value.
17 . The semiconductor device of claim 12 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region; and
a select gate disposed over and insulated from a second portion of the channel region,
wherein the voltage applied to the memory cell is applied to the select gate.
18 . The semiconductor device of claim 12 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region;
a select gate disposed over and insulated from a second portion of the channel region; and
an erase gate disposed over and insulated from the source region,
wherein the voltage applied to the memory cell is applied to the erase gate.
19 . The semiconductor device of claim 12 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region;
a select gate disposed over and insulated from a second portion of the channel region;
an erase gate disposed over and insulated from the source region; and
a control gate disposed over and insulated from the floating gate,
wherein the voltage applied to the memory cell is applied to the erase gate.
20 . The semiconductor device of claim 13 , wherein the memory cell comprises:
a source region and a drain region formed in a semiconductor substrate, with a channel region of the semiconductor substrate extending between the source region and the drain region;
a floating gate disposed over and insulated from a first portion of the channel region;
a select gate disposed over and insulated from a second portion of the channel region;
an erase gate disposed over and insulated from the source region; and
a control gate disposed over and insulated from the floating gate,
wherein the voltage applied to the memory cell is applied to the control gate.