Fully-depleted SOI MOSFETs with low source and drain resistance and minimal overlap capacitance using a recessed channel damascene gate process
View Patent ↗A sub-0.05 μm channel length fully-depleted SOI MOSFET device having low source and drain resistance and minimal overlap capacitance and a method of fabricating the same are provided. The sub-0.05 μm channel length fully-depleted SOI MOSFET device includes an SOI structure which contains at least an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein the second thickness is greater than the first thickness and the source/drain regions having a salicide layer present thereon. A gate region is present also atop the SOI layer.
1. A sub-0.05 μm channel length fully-depleted silicon-on-insulator(SOI) metal oxide semiconductor field effect transistor (MOSFET) device comprising
an SOI layer having a channel region of a first thickness and abutting source/drain regions of a second thickness present therein, wherein said second thickness is greater than said first thickness and said source/drain regions have a salicide layer present thereon; and
at least one gate region present atop said SOI layer, said at least one gate region including a pair of nitride spacers comprising a thick outer nitride spacer and a thinner inner nitride spacer present on vertical sidewalls of said at least one channel region.
2. The sub-0.05 μm channel length fully-depleted SOI MOSFET device of claim 1 wherein said SOI layer is part of an SOI structure, said SOI structure further comprising a bottom Si-containing layer and an insulating layer present atop said bottom Si-containing layer, said SOI layer located atop said insulating layer.
3. The sub-0.05 μm channel length fully-depleted SOI MOSFET device of claim 1 wherein said at least one gate region further includes a gate dielectric and a gate conductor present atop said gate dielectric.
4. The sub-0.05 μn channel length hilly-depleted SOI MOSFET device of claim 3 wherein said gate dielectric comprises SiO 2 , Si 3 N 4 , SiON, TiO 2 , Al 2 O 3 , ZrO 2 , HfO 2 , Ta 2 O 5 , or La 2 O 3 .
5. The sub-0.05 μn channel length hilly-depleted SOI MOSFET device of claim 3 wherein said gate conductor comprises polysilicon; an elemental conductive metal; an alloy of an elemental conductive metal; a silicide or nitride of an elemental conductive metal; or any combination thereof.
6. The sub-0.05 μn channel length filly-depleted SOI MOSFET device of claim 1 wherein said salicide layer comprises Ti silicide, Co suicide or Ni suicide.
7. The sub-0.05 μm channel length fully-depleted SOI MOSFET device of claim 1 wherein said SOI structure further comprises trench isolation regions present therein.
8. The sub-0.05 μm channel length fully-depleted SOI MOSFET device of claim 1 wherein said channel region of said first thickness has a thickness from about 10 to about 20 nm.
9. The sub-0.05 μm channel length fully-depleted SOI MOSFET device of claim 1 further comprising an epitaxial Si layer atop said source/drain regions.
10. The sub-0.05 μm channel length fully-depleted SOI MOSFET device of claim 1 wherein said source/drain regions are self-aligned to said outer nitride spacer.