Apparatus for emulation of electronic systems
A system for physical emulation of electronic circuits or systems includes a data entry workstation where a user may input data representing the circuit or system configuration. This data is converted to a form suitable for programming an array of programmable gate elements provided with a richly interconnected architecture. Provision is made for externally connecting VLSI devices or other portions of a user's circuit or system a network of internal probing interconnections is made available by utilization of unused circuit paths in the programmable gate arrays.
1. A hardware logic emulation system capable of implementing a digital logic design, said digital logic design comprised of combinational and sequential logic elements, comprising:
a printed circuit board;
an array of programmable gate array devices arranged in a matrix on said printed circuit boards, each of said programmable gate array devices adapted to implement a portion of said digital logic design, and each of said programmable gate array devices comprising a plurality of input/output pins;
a plurality of input/output pin conductors, each of said plurality of input/output pin conductors forming a part of said printed circuit board and wherein at least some of said input/output pin conductors are placed in electrical communications with at least some of said input/output pins on each of said programmable gate array devices such that at least some of said input/output pins on said programmable gate array devices are placed in direct electrical communication with other of said programmable gate array devices;
a computer adapted to receive input data representative of said digital logic design and to process said input data into a form that can be implemented in said plurality of programmable gate array devices.
2. The hardware logic emulation system of claim 1 wherein said plurality of programmable integrated circuits comprise identical types of programmable gate array devices.
3. The hardware logic emulation system of claim 1 wherein said computer runs a partitioning program which determines which of said programmable gate array devices are capable of being reserved for interconnecting others of said programmable gate array devices.