System for testing semiconductor die on multiple semiconductor wafers
A system for testing semiconductor die on multiple semiconductor wafers includes a testing unit ( 82 ), a test fixture bank ( 84 ) operably coupled to the testing unit ( 82 ), a plurality of test fixture racks ( 86-92 ) operably coupled to the test fixture bank ( 84 ) and a plurality of wafer-interposer assemblies ( 94-140 ) operably coupled to each of the test fixture racks ( 86-92 ). Each of the wafer-interposer assemblies ( 94-140 ) includes a semiconductor wafer having a plurality of semiconductor die and an interposer coupled to the semiconductor wafer. The interposer has a first set of conductors for electrically connecting the semiconductor die of the semiconductor wafer to a substrate and a second set of conductors that electrically connect the semiconductor die of the semiconductor wafer to the test fixture rack ( 86-92 ) via a connector, thereby providing for addressing and testing of the semiconductor die.
1. A system for testing semiconductor die on multiple semiconductor wafers comprising:
a test fixture rack having connectors; and
at least two wafer-interposer assemblies, the wafer-interposer assemblies each including a semiconductor wafer having a plurality of semiconductor die and an interposer coupled to the semiconductor wafer, the interposer having a first set of conductors for electrically connecting the semiconductor die of the semiconductor wafer to a substrate and a second set of conductors that electrically connect the semiconductor die of the semiconductor wafer to the test fixture rack via one of the connectors, thereby providing for addressing and testing of the semiconductor die.
2. The system as recited in claim 1 wherein the test fixture rack further comprises discrete devices for enhancing testing of the semiconductor die.
3. The system as recited in claim 1 wherein the test fixture rack further comprises display devices that indicate a parameter associated with testing of the semiconductor die.
4. The system as recited in claim 1 wherein the test fixture rack further comprises a handle.
5. The system as recited in claim 1 further comprising at least one positioning guide attached to the test fixture rack.
6. The system as recited in claim 1 wherein the test fixture rack is operably couplable to a testing unit that performs parametric testing of at least a portion of the semiconductor die.
7. The system as recited in claim 1 wherein the test fixture rack is operably couplable to a testing unit that performs sequential testing of at least a portion of the semiconductor die.
8. The system as recited in claim 1 wherein the test fixture rack is operably couplable to a testing unit that performs simultaneous testing of at least a portion of the semiconductor die.
9. The system as recited in claim 1 wherein the test fixture rack is operably couplable to a testing unit that performs vibrational and mechanical stress testing on at least a portion of the semiconductor die.
10. The system as recited in claim 1 wherein the test fixture rack is operably couplable to a test fixture bank.
11. The system as recited in claim 10 wherein test fixture bank is operably couplable to a testing unit.
12. A system for testing semiconductor die on multiple semiconductor wafers comprising:
a test fixture bank;
at least two test fixture racks operably coupled to the test fixture bank, each of the test fixture racks having connectors; and
at least two wafer-interposer assemblies operably coupled to each of the test fixture racks, the wafer-interposer assemblies each including a semiconductor wafer having a plurality of semiconductor die and an interposer coupled to the semiconductor wafer, the interposer having a first set of conductors for electrically connecting the semiconductor die of the semiconductor wafer to a substrate and a second set of conductors that electrically connect the semiconductor die of the semiconductor wafer to the test fixture rack via one of the connectors, thereby providing for addressing and testing of the semiconductor die.
13. The system as recited in claim 12 wherein each of the test fixture racks further comprises discrete devices for enhancing testing of the semiconductor die.
14. The system as recited in claim 12 wherein each of the test fixture racks further comprises display devices that indicate a parameter associated with testing of the semiconductor die.
15. The system as recited in claim 12 wherein each of the test fixture racks further comprises a handle.
16. The system as recited in claim 12 further comprising at least one positioning guide attached to each of the test fixture racks for aligning the test fixture racks with the test fixture bank.
17. The system as recited in claim 12 wherein the test fixture bank is operably couplable to a testing unit that performs parametric testing of at least a portion of the semiconductor die.
18. The system as recited in claim 12 wherein the test fixture bank is operably couplable to a testing unit that performs sequential testing of at least a portion of the semiconductor die.
19. The system as recited in claim 12 wherein the test fixture bank is operably couplable to a testing unit that performs simultaneous testing of at least a portion of the semiconductor die.
20. The system as recited in claim 12 wherein the test fixture bank is operably couplable to a testing unit that performs vibrational and mechanical stress testing on at least a portion of the semiconductor die.
21. A system for testing semiconductor die on multiple semiconductor wafers comprising:
a testing unit;
a test fixture bank operably coupled to the testing unit;
at least two test fixture racks operably coupled to the test fixture bank, each of the test fixture racks having connectors; and
at least two wafer-interposer assemblies operably coupled to each of the test fixture racks, the wafer-interposer assemblies each including a semiconductor wafer having a plurality of semiconductor die and an interposer coupled to the semiconductor wafer, the interposer having a first set of conductors for electrically connecting the semiconductor die of the semiconductor wafer to a substrate and a second set of conductors that electrically connect the semiconductor die of the semiconductor wafer to the test fixture rack via one of the connectors, thereby providing for addressing and testing of the semiconductor die.
22. The system as recited in claim 21 wherein each of the test fixture racks further comprises discrete devices for enhancing testing of the semiconductor die.
23. The system as recited in claim 21 wherein each of the test fixture racks further comprises display devices that indicate a parameter associated with testing of the semiconductor die.
24. The system as recited in claim 21 wherein each of the test fixture racks further comprises a handle.
25. The system as recited in claim 21 further comprising at least one positioning guide attached to each of the test fixture racks for aligning the test fixture racks with the test fixture bank.
26. The system as recited in claim 21 wherein the testing unit performs parametric testing of at least a portion of the semiconductor die.
27. The system as recited in claim 21 wherein the testing unit performs sequential testing of at least a portion of the semiconductor die.
28. The system as recited in claim 21 wherein the testing unit performs simultaneous testing of at least a portion of the semiconductor die.
29. The system as recited in claim 21 wherein the testing unit performs vibrational and mechanical stress testing on at least a portion of the semiconductor die.