Dual steered frequency synthesizer
A frequency synthesizer 100 comprising a charge pump 102 , a loop filter 104 , a loop divider 106 , and an active and dual port VCO 110 . An integrator 108 low pass filters a steering voltage to provide a low frequency path while the steering voltage provides a high frequency path. Both steering paths are connected to dual port VCO 110 . The dual port VCO 110 is a single frequency generator which is controlled by two control signals. The dual port VCO 110 , effectively provides the equivalent of a low frequency path 114 and a high frequency noise compensation path 112 , both paths effectively merging 116 by superposition.
1. A frequency synthesizer comprising:
a charge pump receiving a difference signal and providing an error compensation charge sample in response to said difference signal;
loop filter filtering said error compensation charge sample to provide a control voltage;
a dual port voltage control oscillator (VCO) receiving said control voltage from said loop filter, wherein said dual port VCO comprises at least one pair of transconductance inverting amplifiers cross coupled and providing at least a pair of complementary outputs;
an integrator comparing said control voltage to a reference voltage and providing an integrated error compensation voltage to said dual port VCO in response to said comparison, said dual port VCO providing an output frequency determined by said control voltage and said integrated error compensation voltage; and
a frequency divider dividing said output frequency by at least unity, said difference signal resulting from an input reference signal being combined with said divided frequency.
2. A frequency synthesizer as in claim 1 wherein said dual port VCO comprises:
a first pair of voltage controllable transconductance inverting amplifiers cross coupled and providing a first pair of complementary outputs;
a second pair of voltage controllable transconductance inverting amplifiers cross-coupled and providing a second pair of complementary outputs said second pair of complementary outputs being ninety degrees out of phase with said first pair of complementary outputs;
a third pair of voltage controllable transconductance inverting amplifiers connected in series between outputs of said first pair, an output of said second pair connected between said third pair; and
a fourth pair of voltage controllable transconductance inverting amplifiers connected in series between outputs of said second pair, an output of said first pair being connected between said fourth pair, transconductance of amplifiers in said first and second pair being controlled by a first control voltage and transconductance of amplifiers in said third and fourth pair being controlled by a second control voltage.
3. A frequency synthesizer as in claim 2 , wherein two pair of controllable transconductance inverting amplifiers in said dual port VCO are pairs of inverters, transconductance of said pairs of inverters being controlled by adjusting an inverter supply voltage.
4. A frequency synthesizer as in claim 3 , each of said controllable transconductance inverting amplifiers in said dual port VCO comprising:
a first field effect transistor (FET) connected between a high supply voltage Vhi and an inverting output, said first FET being a p-type FET (PFET); and
an n-type FET (NFET) connected between a low supply voltage and said inverting output.
5. A frequency synthesizer as in claim 4 , wherein two other pair of said controllable transconductance inverting amplifiers further comprise:
a second PFET connected between Vhi and said first PFET, said filtered control voltage being provided to a control gate of said second PFET;
a third and fourth PFET connected in series and between Vhi and said output, said noise difference voltage being provided to a control gate of said fourth PFET; and
a VCO phase being connected to a control gate of said NFET, said first PFET and said third PFET.
6. A frequency synthesizer as in claim 5 wherein said integrator comprises:
a differential amplifier;
a capacitor connected between said differential amplifier output and a negative input to said differential amplifier; and
a resistor connected between an input to said integrator and said negative input of said differential amplifier, an output of said differential amplifier being the output of said integrator.
7. A frequency synthesizer as in claim 5 wherein said integrator comprises:
a comparator comparing said filtered control voltage against a threshold voltage;
an up/down counter receiving an output of said comparator, said up/down counter incrementing or decrementing in response to said comparator output; and
a digital to analog converter converting a count output of said up/down counter to an integrator output voltage.
8. A frequency synthesizer as in claim 5 wherein said loop filter comprises:
a series resistor and capacitor (RC) connected between an output of said charge pump and a reference voltage; and
a capacitor in parallel with said series RC.
9. A frequency synthesizer as in claim 8 wherein said charge pump comprises:
a first current source providing a first current for pumping charge to said loop filter;
a PFET selectively connecting said first current source to said loop filter;
a second current source providing a second current for pumping charge from said loop filter; and
a NFET selectively connecting said second current source to said loop filter, whereby said charge pump maintains said filtered control voltage at said loop filter.
10. A closed loop frequency synthesizer comprising:
a charge pump receiving a difference signal and providing an error compensation charge sample in response to said difference signal;
a loop filter filtering said error compensation charge sample to provide a control voltage;
a dual port voltage control oscillator (VCO) receiving said control voltage from said loop filter, said dual port VCO comprising:
a first pair of voltage controllable transconductance inverting amplifiers cross coupled and providing a first pair of complementary output,
a second pair of voltage controllable transconductance inverting amplifiers cross-coupled and providing a second pair of complementary outputs, said second pair of complementary outputs being ninety degrees out of phase with said first pair of complementary outputs,
a third pair of voltage controllable transconductance inverting amplifiers connected in series between outputs of said first pair, an output of said second pair connected between said third pair, and
a fourth pair of voltage controllable transconductance inverting amplifiers connected in series between outputs of said second pair, an output of said first pair being connected between said fourth pair, transconductance of amplifiers in said first and second pair being controlled by a first control voltage and transconductance of amplifiers in said third and fourth pair being controlled by a second control voltage;
an integrator comparing said control voltage to a reference voltage and providing an integrated error compensation voltage to said dual port VCO in response to said comparison, said control voltage and said integrated error compensation voltage controlling transconductance in two pair of said voltage controllable transconductance amplifiers, said dual port VCO providing an output frequency determined by said control voltage and said integrated error compensation voltage; and
a frequency divider dividing said output frequency by at least unity, said difference signal resulting from an input reference signal being combined with said divided frequency.
11. A closed loop frequency synthesizer as in claim 10 , each of said voltage controllable transconductance inverting amplifiers in said dual port VCO comprising:
a first P-type field effect transistor (PFET) connected between a high supply voltage Vhi and an inverting amplifier output; and
an n-type FET (NFET) connected between a low supply voltage and said inverting amplifier output.
12. A closed loop frequency synthesizer as in claim 11 , wherein said two pair of voltage controllable transconductance inverting amplifiers further comprise:
a second PFET connected between Vhi and said first PFET, said filtered control voltage being provided to a control gate of said second PFET;
a third and fourth PFET connected in series and between Vhi and said output, said noise difference voltage being provided to a control gate of said fourth PFET; and
a VCO phase being connected to a control gate of said NFET, said first PFET and said third PFET.
13. A closed loop frequency synthesizer as in claim 12 , wherein said two pair are said first pair and said second pair.
14. A closed loop frequency synthesizer as in claim 12 , wherein said two pair are said third pair and said fourth pair.
15. A closed loop frequency synthesizer as in claim 12 , wherein said integrator comprises:
a differential amplifier;
a capacitor connected between said differential amplifier output and a negative input to said differential amplifier; and
a resistor connected between an input to said integrator and said negative input of said differential amplifier, an output of said differential amplifier being the output of said integrator.
16. A closed loop frequency synthesizer as in claim 12 wherein said integrator comprises:
a comparator comparing said filtered control voltage against a threshold voltage;
an up/down counter receiving an output of said comparator, said up/down counter incrementing or decrementing in response to said comparator output; and
a digital to analog converter converting a count output of said up/down counter to an integrator output voltage.
17. A closed loop frequency synthesizer as in claim 12 , wherein said loop filter comprises:
a series resistor and capacitor (RC) connected between an output of said charge pump and a reference voltage; and
a capacitor in parallel with said series RC.
18. A closed loop frequency synthesizer as in claim 17 , wherein said charge pump comprises:
a first current source providing a first current for pumping charge to said loop filter;
a PFET selectively connecting said first current source to said loop filter;
a second current source providing a second current for pumping charge from said loop filter; and
a NFET selectively connecting said second current source to said loop filter, whereby said charge pump maintains said filtered control voltage at said loop filter.