Damascene integration scheme for developing metal-insulator-metal capacitors
View Patent ↗The invention is directed to unique high-surface area BEOL capacitor structures with high-k dielectric layers and methods for fabricating the same. These high-surface area BEOL capacitor structures may be used in analog and mixed signal applications. The capacitor is formed within a trench with pedestals within the trench to provide additional surface area. The top and bottom electrodes are created using damascene integration scheme. The dielectric layer is created as a multilayer dielectric film comprising for instance Al 2 O 3 , Al 2 O 3 /Ta 2 O 5 , Al 2 O 3 /Ta 2 O 5 /Al 2 O 3 and the like. The dielectric layer may be deposited by methods like atomic layer deposition or chemical vapor deposition. The dielectric layer used in the capacitor may also be produced by anodic oxidation of a metallic precursor to yield a high dielectric constant oxide layer.
1. A capacitor comprising:
a first inter-level dielectric on a substrate;
a first trench in said first inter-level dielectric;
a first conductive material within said first trench;
a second inter-level dielectric residing over said first inter-level dielectric and a portion of said conductive material;
a second trench in said second inter-level dielectric, said second trench residing over and exposing a portion of said first conductive material;
a second conductive material within said second trench to provide a conductive pedestal directly over said exposed portion of said first conductive material, said conductive pedestal increasing surface area of said capacitor thereby enabling said capacitor to have a significantly higher capacitance, said first conductive material and said conductive pedestal together forming a continuous conductive feature; and
a first electrode of said capacitor comprising said continuous conductive feature.
2. The capacitor of claim 1 further including a cap layer residing between said first and second inter-level dielectric layers.
3. The capacitor of claim 2 further including:
a first barrier layer over exposed portions of said conductive pedestal and an area over said continuous conductive feature;
at least one high-k dielectric layer over said barrier layer;
a second barrier layer over said at least one high-k dielectric layer;
a conductive metal layer over said second barrier layer and filling said area; and
a second cap layer over a portion of said conductive metal layer and continuous with said first cap layer to isolate said conductive metal layer together forming a second electrode of said capacitor from said first electrode of said capacitor comprising continuous conductive feature.
4. The capacitor of claim 1 wherein said first and second conductive materials comprise the same conductive material.
5. The capacitor of claim 1 wherein said first and second conductive materials comprise different conductive materials.
6. The capacitor of claim 5 further including a barrier layer lining sidewalls of said first trench and said second trench.
7. The capacitor of claim 1 wherein said at least one high-k dielectric layer comprises a single-layer high-k dielectric.
8. The capacitor of claim 1 wherein said at least one high-k dielectric layer comprises a multi-layer high-k dielectric layer.
9. The capacitor of claim 8 wherein said at least one multi-layer high-k dielectric layer comprises a top low-leakage dielectric layer, a middle high-k dielectric layer and a bottom low-leakage dielectric layer.
10. The capacitor of claim 1 wherein said at least one high-k dielectric layer is selected from the group consisting of Nb 2 O 5 , TiO 2 , WO 3 , Y 2 O 3 , ZrO 3 , Al 2 O 3 , Si 3 N 4 , Ta 2 O 5 , SiO 2 , HfO 2 , and combinations thereof.
11. The capacitor of claim 1 wherein said capacitor comprises a plurality of conductive pedestals having a variety of shapes and sizes to further maximize surface area of said capacitor.
12. A capacitor comprising:
a first inter-level dielectric on a substrate having a first trench filled with a first conductive material;
a second inter-level dielectric over said first inter-level dielectric having a second trench over and smaller in dimension than said first trench filled with a second conductive material to provide a conductive pedestal directly over said first conductive material to provide a continuous conductive feature;
a first barrier layer lining an area over said continuous conductive feature and covering exposed portions of said conductive pedestal within said area;
at least one high-k dielectric layer over said barrier layer;
a second barrier layer over said at least one high-k dielectric layer;
a conductive metal layer over said second barrier layer and filling said area; and
a continuous cap layer residing between said first and second inter-level dielectric layers and over a portion of said conductive metal layer to isolate said conductive metal layer;
a top electrode of said capacitor comprising said conductive metal layer; and
a bottom electrode of said capacitor comprising said continuous conductive feature, whereby said conductive pedestal of said continuous conductive feature increases surface area of said capacitor thereby enabling said capacitor to have a significantly higher capacitance.
13. The capacitor of claim 12 wherein said conductive pedestal of said bottom electrode increases surface area of the capacitor to increase said capacitance as a function of:
C=ε 0 ε r d/A,
whereby said capacitance “C” is equal to permitivity of the free space “ε 0 =8.85.×.10 −14 F/cm” multiplied by relative permitivity “ε r ” multiplied by thickness of said at least one high-k dielectric layer divided by surface area of said substrate “A”.
14. The capacitor of claim 13 wherein said capacitor further comprises a plurality of conductive pedestals having a variety of shapes and sizes to further increase surface area of said capacitor.