IP Library Granted Patent US 7,013,222
Granted Patent B2
US 7,013,222 · App. 10/661,013 · Granted Mar 14, 2006

Wafer edge inspection data gathering

Assignee: LSI Logic Corporation
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Quick Facts
Patent No.
US 7,013,222
App. No.
10/661,013
Granted
Mar 14, 2006
Kind
B2
Abstract

A wafer edge inspection method and apparatus include a review tool that captures images of the semiconductor wafer. According to various embodiments, the present invention also includes a map of points of interest proximate to the edge of the wafer, automatic image capturing at the points of interest, fake defect locations defining the points of interest, a database in which the images are stored and computer-searchable for detailed defect analysis, a software tool for controlling the method and apparatus and/or context information identifying the points of interest, the inspected wafer and/or the fabrication station/step preceding the inspection.

Claims (84)

1. A method of gathering semiconductor wafer edge inspection data, wherein a review tool captures images of the semiconductor wafer, comprising:

providing a semiconductor wafer;

generating a map of points of interest proximate to an edge of the semiconductor wafer;

identifying the points of interest with location identifiers for fake defects at the points of interest;

supplying the points of interest to the review tool in automatic succession;

instructing the review tool to capture images at the points of interest;

automatically storing the captured images; and

correlating the captured images with the points of interest.

2. A method as defined in claim 1 further comprising:

generating context information for the captured images identifying the semiconductor wafer; and

correlating the captured images with the context information.

3. A method of gathering semiconductor wafer edge inspection data, wherein a review tool captures images of the semiconductor wafer, the review tool is incorporated in a semiconductor fabrication system having a plurality of fabrication stations for performing fabrication steps on the semiconductor wafer, and the review tool is situated subsequent to a preceding one of the fabrication stations, comprising:

providing a semiconductor wafer;

generating a map of points of interest proximate to an edge of the semiconductor wafer;

supplying the points of interest to the review tool in automatic succession;

instructing the review tool to capture images at the points of interest;

automatically storing the captured images;

correlating the captured images with the points of interest;

generating first context information for the captured images identifying the semiconductor wafer;

correlating the captured images with the first context information;

generating second context information for the captured images identifying the preceding fabrication station; and

correlating the captured images with the second context information.

4. A method of gathering semiconductor wafer edge inspection data, wherein a review tool captures images of the semiconductor wafer, comprising:

providing a semiconductor wafer;

generating points of interest proximate to an edge of the semiconductor wafer by identifying fake defects with fake defect identifiers;

causing the review tool to capture images at the points of interest by instructing the review tool to capture the images at the fake defects identified by the fake defect identifiers; and

storing the captured images.

5. A method as defined in claim 4 wherein the review tool captures images of the semiconductor wafer through a view finder and can drive the view finder to an identified defect location, further comprising:

supplying the fake defect identifiers to the review tool; and

instructing the review tool to drive the view finder to the fake defects identified by the fake defect identifiers and to capture images at the fake defects.

6. A method as defined in claim 5 further comprising:

correlating the captured images with the points of interest according to the fake defect at which each captured image was captured.

7. A method as defined in claim 4 further comprising:

generating context information including information identifying the semiconductor wafer; and

correlating the captured images with the context information.

8. A method of gathering semiconductor wafer edge inspection data, wherein a review tool captures images of the semiconductor wafer, the review tool is incorporated in a semiconductor fabrication system having a plurality of fabrication stations for performing fabrication steps on the semiconductor wafer, and the review tool is situated subsequent to a preceding one of the fabrication stations, comprising:

providing a semiconductor wafer;

generating first context information including information identifying the semiconductor wafer;

generating a map of points of interest proximate to an edge of the semiconductor wafer;

instructing the review tool to capture images at the points of interest;

storing the captured images;

correlating the captured images with the points of interest and the first context information;

generating second context information for the captured images identifying the preceding fabrication station; and

correlating the captured images with the second context information.

9. A method as defined in claim 8 further comprising:

storing the context information in a computer-searchable manner.

10. A method as defined in claim 8 wherein the semiconductor wafer edge inspection data is gathered by a software tool, further comprising:

the software tool instructing the review tool to capture the images at the points of interest; and

the software tool correlating the captured images with the points of interest and the context information.

11. A method of gathering semiconductor wafer edge inspection data, wherein a review tool captures images of the semiconductor wafer, the semiconductor wafer edge inspection data is gathered by a software tool, the review tool is incorporated in a semiconductor fabrication system having a plurality of fabrication stations for performing fabrication steps on the semiconductor wafer, and the review tool is situated subsequent to a preceding one of the fabrication stations, comprising:

providing a semiconductor wafer;

generating first context information including information identifying the semiconductor wafer;

generating a map of points of interest proximate to an edge of the semiconductor wafer;

the software tool instructing the review tool to capture images at the points of interest;

storing the captured images;

the software tool correlating the captured images with the points of interest and the first context information;

generating second context information for the captured images identifying the preceding fabrication station; and

the software tool correlating the captured images with the second context information.

12. A system for automated inspection of a semiconductor wafer edge comprising:

a review tool having an image capturing device capable of capturing an image of the semiconductor wafer edge;

a software tool connected to the review tool to supply instructions to the review tool to capture an image at a point of interest proximate to the semiconductor wafer edge and to receive the captured image from the review tool; and

a database connected to the software tool to receive and store the captured image from the software tool and context information identifying the semiconductor wafer, the context information being correlated with the captured image;

and wherein:

the review tool is capable of capturing the image at a predetermined defect location;

the point of interest is indicated by a predetermined fake defect location identified by a fake defect identifier;

the instructions supplied from the software tool to the review tool include the fake defect identifier; and

the review tool captures the image at the predetermined fake defect location.

13. A system for automated inspection of a semiconductor wafer edge as defined in claim 12 wherein:

the review tool is capable of driving the image capturing device to the predetermined defect location; and

the review tool drives the image capturing device to the predetermined fake defect location identified by the fake defect identifier in order to capture the image at the predetermined fake defect location.

14. A system for automated inspection of a semiconductor wafer edge as defined in claim 12 wherein:

the context information correlated with the captured image includes the point of interest according to the predetermined fake defect location at which the captured image was captured.

15. A system for automated inspection of a semiconductor wafer edge as defined in claim 12 wherein:

the database, including the context information, is computer-searchable.

16. A system for automated inspection of a semiconductor wafer edge as defined in claim 12 wherein:

the instructions supplied from the software tool to the review tool include a plurality of points of interest at which the review tool captures a plurality of images in automatic succession; and

the software tool automatically receives and stores the captured images in the database correlated with the context information for each image.

17. A system for automated inspection of a semiconductor wafer edge for use in a fabrication system having a plurality of fabrication stations including a preceding fabrication station, comprising:

a review tool having an image capturing device capable of capturing an image of the semiconductor wafer edge;

a software tool connected to the review tool to supply instructions to the review tool to capture an image at a point of interest proximate to the semiconductor wafer edge and to receive the captured image from the review tool; and

a database connected to the software tool to receive and store the captured image from the software tool and context information identifying the semiconductor wafer, the context information being correlated with the captured image;

and wherein:

the review tool is situated in the fabrication system subsequent to the preceding fabrication station; and

the context information further identifies the preceding fabrication station.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0719 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0608 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 12, 2003
From: STRADER, NATHAN N.
To: LSI LOGIC CORPORATION
Reel/Frame 014511/0856 →
Continuity (1)
Related Publication 20050060104A1 · Mar 17, 2005