IP Library › Granted Patent US 7,062,737
Granted Patent B2
US 7,062,737 · App. 10/901,841 · Granted Jun 13, 2006

Method of automated repair of crosstalk violations and timing violations in an integrated circuit design

Assignee: LSI Logic Corporation
View Patent ↗
Loading inventors, assignments & file history…
Monitor This Case
Get email alerts when status or documents change.
Order Certified Copies
Most orders are placed with the USPTO same day — all within 24 business hours.
Order via The Patent Place →
Pre-filled with this patent's details
Quick Facts
Patent No.
US 7,062,737
App. No.
10/901,841
Granted
Jun 13, 2006
Kind
B2
Abstract

A method and computer program are disclosed for automatically repairing crosstalk violations in an integrated circuit design that include steps of: (a) receiving as input an integrated circuit design; (b) performing an initial cell placement and global routing from the integrated circuit design; (c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing; (d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c); (e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and (f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

Claims (34)

1. A method comprising steps of:

(a) receiving as input an integrated circuit design;

(b) performing an initial cell placement and global routing from the integrated circuit design;

(c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing;

(d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c);

(e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and

(f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

2. The method of claim 1 wherein the first set of rules includes identifying time critical nets and time non-critical nets.

3. The method of claim 1 wherein the additional crosstalk protection includes increasing spacing between the nets having crosstalk violations and aggressor nets.

4. The method of claim 1 wherein the second set of rules includes identifying noise critical nets having noise violations, noise non-critical nets having noise violations, noise critical nets having timing violations, and noise non-critical nets having timing violations.

5. The method of claim 1 wherein the second set of rules includes identifying noise critical nets having noise violations, noise non-critical nets having noise violations, time critical nets with multiple factor violations, and time non-critical nets with multiple factor violations.

6. The method of claim 5 wherein the time critical nets with multiple factor violations and the time non-critical nets with multiple factor violations are identified by determining whether a net length ratio exceeds a selected critical length ratio and a selected non-critical length ratio.

7. The method of claim 6 wherein the time critical nets with multiple factor violations and the time non-critical nets with multiple factor violations are identified by determining whether a net coupling capacitance ratio exceeds a selected critical coupling capacitance ratio and a selected non-critical coupling capacitance ratio.

8. The method of claim 7 wherein the time critical nets with multiple factor violations and the time non-critical nets with multiple factor violations are identified by determining whether a noise glitch peak magnitude ratio exceeds a selected critical noise glitch peak magnitude ratio and a selected non-critical noise glitch peak magnitude ratio.

9. The method of claim 1 further comprising a step of implementing changes to the integrated circuit design from an engineering change order prior to step (f).

10. The method of claim 1 wherein step (c) further comprises a step of identifying nets having timing violations.

11. The method of claim 10 wherein step (d) further comprises a step of performing a detailed routing that includes providing special rule routing for the nets having timing violations.

12. A computer program product for automatically repairing crosstalk violations in an integrated circuit design comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:

(a) receiving as input an integrated circuit design;

(b) performing an initial cell placement and global routing from the integrated circuit design;

(c) identifying nets having crosstalk violations according to a first set of rules from the initial cell placement and global routing;

(d) performing a detailed routing that includes providing crosstalk protection for the nets identified in step (c);

(e) identifying nets having crosstalk violations according to a second set of rules from the detailed routing; and

(f) performing an additional detailed routing that includes providing crosstalk protection for the nets identified in step (e).

13. The computer program product of claim 12 wherein the first set of rules includes identifying time critical nets and time non-critical nets.

14. The computer program product of claim 12 wherein the additional crosstalk protection includes increasing spacing between the nets having crosstalk violations and aggressor nets.

15. The computer program product of claim 12 wherein the second set of rules includes identifying noise critical nets having noise violations, noise non-critical nets having noise violations, noise critical nets having timing violations, and noise non-critical nets having timing violations.

16. The computer program product of claim 12 wherein the second set of rules includes identifying noise critical nets having noise violations, noise non-critical nets having noise violations, multiple factor time critical nets, and time critical nets with multiple factor violations and time non-critical nets with multiple factor violations.

17. The computer program product of claim 16 wherein the time critical nets with multiple factor violations and the time non-critical nets with multiple factor violations are identified by determining whether a net length ratio exceeds a selected critical length ratio.

18. The computer program product of claim 17 wherein the time critical nets with multiple factor violations and the time non-critical nets with multiple factor violations are identified by determining whether a net coupling capacitance ratio exceeds a selected critical coupling capacitance ratio.

19. The computer program product of claim 18 wherein the time critical nets with multiple factor violations and the time non-critical nets with multiple factor violations are identified by determining whether a noise glitch peak magnitude ratio exceeds a selected critical noise glitch peak magnitude ratio and a selected non-critical noise glitch peak magnitude ratio.

20. The computer program product of claim 18 further comprising a step of implementing changes to the integrated circuit design from an engineering change order prior to step (f).

21. The computer program product of claim 12 wherein step (c) further comprises a step of identifying nets having timing violations.

22. The computer program product of claim 21 wherein step (d) further comprises a step of performing a detailed routing that includes providing special rule routing for the nets having timing violations.

Assignments (10)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 28, 2004
From: TETELBAUM, ALEXANDER; MOLINA, RUBEN
To: LSI LOGIC CORPORATION
Reel/Frame 015645/0868 →
Continuity (1)
Related Publication 20060026539A1 · Feb 2, 2006