IP Library Granted Patent US 7,253,497
Granted Patent B2
US 7,253,497 · App. 10/614,307 · Granted Aug 7, 2007

Integrated circuit with inductor having horizontal magnetic flux lines

Assignee: LSI Corporation
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Quick Facts
Patent No.
US 7,253,497
App. No.
10/614,307
Granted
Aug 7, 2007
Kind
B2
Abstract

An integrated circuit (IC) includes one or more inductors that have magnetic flux lines substantially parallel to a generally horizontal plane of the IC. The inductor is formed in a plurality of conductor layers separated by insulating layers of the IC. Regions of highest magnetic flux density of the inductor may preferably be located near the edge of the IC. Additionally, the inductor may preferably be segmented. The over-all inductance may preferably be controlled by turning on and off selected inductors or inductor segments.

Claims (27)

1. An integrated circuit comprising:

conductor layers arranged substantially parallel to an x-y plane of the integrated circuit;

insulating layers disposed between the conductor layers; and

an inductor formed within the conductor layers and the insulating layers and having magnetic flux lines through the conductor layers substantially parallel to the x-y plane of the integrated circuit upon operation of the integrated circuit, having first and second opposite ends, having a substantially straight length between the first and second opposite ends, and having first and second segments;

and wherein:

the second segment is electrically connected to, proximate to and spaced apart from the first segment;

the first segment of the inductor has a coil-shape in a first spiraling angular direction; and

the second segment of the inductor has a coil-shape in a second spiraling angular direction.

2. An integrated circuit comprising:

conductor layers arranged substantially oarallel to an x-y plane of the integrated circuit;

insulating layers disposed between the conductor layers;

an inductor formed within the conductor layers and the insulating layers and having magnetic flux lines through the conductor layers substantially parallel to the x-y plane of the integrated circuit upon operation of the integrated circuit, having first and second opposite ends, having a substantially straight length between the first and second opposite ends, and having a first segment and a second segment electrically connected to, proximate to and spaced apart from the first segment;

other electronic components disposed under the conductor layers and the insulating layers; and

electrical conductors disposed in the conductor layers between the first segment and second segment of the inductor, the electrical conductors electrically connecting the other electronic components.

3. An integrated circuit comprising:

conductor layers arranged substantially parallel to an x-y plane of the integrated circuit;

insulating layers disposed between the conductor layers:

an inductor formed within the conductor layers and the insulating layers and having magnetic flux lines through the conductor layers substantially parallel to the x-y plane of the integrated circuit upon operation of the integrated circuit, having first and second opposite ends, and having a substantially straight length between the first and second opposite ends; and

an edge of the integrated circuit;

and wherein the first end of the inductor is proximate to the edge of the integrated circuit.

4. An integrated circuit as defined in claim 3 wherein the aforementioned edge of the integrated circuit is a first edge, further comprising:

a second edge of the integrated circuit opposite the first edge;

and wherein;

the first end of the inductor is proximate to the first edge of the integrated circuit; and

the second end of the inductor is proximate to the second edge of the integrated circuit.

5. An integrated circuit as defined in claim 3 wherein;

the magnetic flux lines of the inductor have a greatest density at the end of the inductor proximate to the edge of the integrated circuit upon operation of the integrated circuit.

Assignments (10)
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2003
From: BHATT, HEMANSHU D.; FURE, JAN; ALLMAN, DERRYL D.J.
To: LSI LOGIC CORPORATION
Reel/Frame 014296/0837 →
Continuity (1)
Related Publication 20050003562A1 · Jan 6, 2005