Voltage controlled static random access memory
View Patent ↗A static random access memory (SRAM) ( 200, 400 ) comprising a plurality of SRAM cells ( 204 ), a plurality of wordlines (WL 0 -WLN) and a voltage regulator ( 240, 240′, 300, 516 ) for driving the wordlines with a wordline voltage signal (VWLP). The wordline voltage signal is determined so as to reduce the likelihood of occurrence of read-disturbances and other memory instabilities. In one embodiment, the wordline voltage signal is determined as a function of the metastability voltage (VMETA) of the SRAM cells and an adjusted most positive down level voltage (VAMPDL) that is a function of a predetermined voltage margin (VM) and a most positive down level voltage (VMPDL) that corresponds to the read-disturb voltage of the SRAM cells.
1. A method of driving a wordline of a static random access memory (SRAM) comprising at least one SRAM cell, comprising the steps of:
a) determining a metastability voltage of the at least one SRAM cell; and
b) generating a wordline voltage signal as a function of said metastability voltage;
wherein step a) includes electrically connecting together a pair of internal voltage nodes of an SRAM cell.
2. A method according to claim 1 , further comprising the step of feeding back said wordline voltage signal as a feed-back wordline voltage signal, step b) including generating said wordline voltage signal as a function of said metastability voltage and said feed-back wordline voltage signal.
3. A method according to claim 1 , further comprising the step of generating an adjusted most positive down level voltage signal, step b) including generating said wordline voltage signal as a function of said metastability voltage and said adjusted most positive down level voltage.
4. A method according to claim 3 , wherein the step of generating an adjusted most positive down level voltage comprises adding a voltage margin signal to a most positive down level voltage.
5. A method of driving a wordline of a static random access memory (SRAM) comprising at least one SRAM cell, comprising the steps of:
a) determining a metastability voltage of the at least one SRAM cell;
b) generating an adjusted most positive down level voltage signal; and
c) generating a wordline voltage signal as a function of said metastability voltage and said adjusted most positive down level voltage.
6. A method according to claim 5 , wherein step b) comprises adding a voltage margin signal to a most positive down level voltage.