Low-temperature metal-induced crystallization of silicon-germanium films
The present invention provides for a low-temperature method to crystallize a silicon-germanium film. Metal-induced crystallization of a deposited silicon film can serve to reduce the temperature required to crystallize the film. Increasing germanium content in a silicon-germanium alloy further decreases crystallization temperature. By using metal-induced crystallization to crystallize a deposited silicon-germanium film, temperature can be reduced substantially. In preferred embodiments, for example in a monolithic three dimensional array of stacked memory levels, reduced temperature allows the use of aluminum metallization. In some embodiments, use of metal-induced crystallization in a vertically oriented silicon-germanium diode having conductive contacts at the top and bottom end is be particularly advantageous, as increased solubility of the metal catalyst in the contact material will reduce the risk of metal contamination of the diode.
1. A method for crystallizing a semiconductor film, the method comprising:
depositing a film of a silicon-germanium alloy at a temperature below about 490 degrees C.;
depositing a layer of a metal catalyst selected from the group consisting of nickel, cobalt, ruthenium, and aluminum, the metal catalyst in contact with the silicon-germanium film; and
crystallizing the silicon-germanium alloy film at a temperature below about 490 degrees C.
2. The method of claim 1 wherein the silicon-germanium alloy is between about 5 and about 50 atomic percent germanium.
3. The method of claim 2 wherein the silicon-germanium alloy is between about 10 and about 30 atomic percent germanium.
4. The method of claim 1 wherein the metal is nickel.
5. The method of claim 1 wherein, during the crystallizing step, the temperature is about 480 degrees C. or below.
6. The method of claim 1
wherein, before the crystallizing step, the silicon-germanium film comprises an n-doped or p-doped first region, and
wherein the n-doped or p-doped first region is crystallized during the crystallizing step.
7. The method of claim 6
wherein, before the crystallizing step, the silicon-germanium film comprises an n-doped first region and a p-doped second region, the first region and second region not overlapping, and
wherein the first region and the second region are crystallized during the crystallizing step.
8. The method of claim 7 wherein the n-doped first region is above or below the p-doped second region.
9. The method of claim 1 further comprising, after the step of depositing the metal catalyst and before the crystallizing step, annealing to react the metal catalyst with the silicon-germanium alloy to form a silicide-germanide.
10. The method of claim 1 further comprising patterning and etching the silicon-germanium film to form a plurality of pillars.
11. The method of claim 10 wherein the each pillar comprises a vertically oriented semiconductor junction diode.
12. The method of claim 1 wherein the silicon-germanium film is deposited above a monocrystalline semiconductor substrate and above aluminum metallization, the aluminum metallization disposed between the silicon-germanium film and the monocrystalline semiconductor.
13. The method of claim 1 wherein, during the crystallization step, a crystallization front comprising atoms of the metal catalyst advances through the silicon-germanium film.
14. A method for forming a first memory level comprising a plurality of first memory cells, the method comprising:
depositing a film of a silicon-germanium alloy at a temperature below about 490 degrees C.;
depositing a layer of a metal catalyst selected from the group consisting of nickel and aluminum, the metal catalyst in contact with the silicon-germanium film;
crystallizing the silicon-germanium alloy film at a temperature not exceeding about 490 degrees C.; and
forming the first memory cells, wherein each memory cell comprises a portion of the silicon-germanium alloy film.
15. The method of claim 14 wherein, during the crystallizing step, the temperature does not exceed about 480 degrees C.
16. The method of claim 14 , wherein the silicon-germanium alloy is between about 5 and about 50 atomic percent germanium.
17. The method of claim 16 wherein the silicon-germanium alloy is between about 15 and about 25 percent germanium.
18. The method of claim 14 wherein the step of forming the first memory cells comprises patterning and etching the silicon-germanium alloy film to form first pillars.
19. The method of claim 18 wherein the each memory cell comprises one of the first pillars, and wherein each first pillar comprises a vertically oriented semiconductor junction diode.
20. The method of claim 19 wherein each memory cell further comprises a resistance-switching element arranged electrically in series with the diode.
21. The method of claim 20 wherein the resistance-switching element comprises a layer of a resistivity-switching metal oxide or nitride compound, the metal oxide or nitride compound including exactly one metal, the layer of the metal oxide or nitride compound arranged electrically in series with the diode.
22. The method of claim 21 wherein the metal oxide or nitride compound is selected from the group consisting of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and A x IN y .
23. The method of claim 19 wherein each memory cell further comprises a dielectric rupture antifuse, the dielectric rupture antifuse arranged electrically in series with the diode.
24. The method of claim 14 wherein each memory cell comprises a field effect transistor, and wherein a channel region of the field effect transistor comprises a portion of the silicon-germanium alloy film.
25. The method of claim 14 wherein, during the crystallization step, a crystallization front comprising atoms of the metal catalyst advances through the silicon-germanium alloy film.
26. The method of claim 14 wherein the silicon-germanium alloy film is deposited above a semiconductor substrate.
27. The method of claim 26 further comprising, before the step of depositing the silicon-germanium alloy film, forming aluminum metallization above the semiconductor substrate.
28. A method for forming a monolithic three dimensional memory array, the method comprising:
a) monolithically forming a first memory level above a substrate by a method comprising:
i) depositing an amorphous film of a silicon-germanium alloy;
ii) depositing a metal catalyst in contact with the silicon-germanium alloy film, the metal catalyst selected from the group consisting of nickel and aluminum;
iii) annealing to crystallize the silicon-germanium alloy film, wherein during the steps of depositing and annealing the silicon-germanium alloy film, the temperature does not exceed about 490 degrees C.;
iv) forming a first plurality of memory cells, each memory cell comprising a portion of the silicon-germanium alloy film, the first memory level comprising the first plurality of memory cells; and
b) monolithically forming a second memory level above the first memory level.
29. The method of claim 28 wherein, during the steps of depositing and annealing the silicon-germanium alloy film, the temperature does not exceed about 480 degrees C.
30. The method of claim 28 , wherein the silicon-germanium alloy is between about 10 and about 30 atomic percent germanium.
31. The method of claim 28 wherein the first memory level further comprises a first plurality of substantially parallel, substantially coplanar rail-shaped conductors comprising aluminum.
32. The method of claim 28 wherein the step of forming the first memory level further comprises patterning and etching the silicon-germanium alloy film to form first pillars.
33. The method of claim 32 wherein each first pillar comprises a vertically oriented diode, wherein each first memory cell comprises one of the first pillars.
34. The method of claim 33 wherein each first memory cell further comprises a resistance-switching element arranged in series with the diode.
35. The method of claim 34 wherein each resistance switching element comprises a layer of a resistivity-switching metal oxide or nitride compound, the metal oxide or nitride compound including exactly one metal, the layer of the metal oxide or nitride compound arranged electrically in series with the diode.
36. The method of claim 35 wherein the metal oxide or nitride compound is selected from the group consisting of Ni x O y , Nb x O y , Ti x O y , Hf x O y , Al x O y , Mg x O y , Co x O y , Cr x O y , V x O y , Zn x O y , Zr x O y , B x N y , and A x IN y .
37. The method of claim 33 wherein each memory cell further comprises a dielectric rupture antifuse, the dielectric rupture antifuse arranged electrically in series with the diode.
38. The method of claim 28 wherein each of the first memory cells comprises a field effect transistor, wherein a channel region of the field effect transistor comprises a portion of the silicon-germanium alloy film.